weight.vhd

来自「完整的TPC编译码VHDL程序」· VHDL 代码 · 共 159 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY weight IS
PORT
(clk		                        : IN   STD_LOGIC;
 start                              : in   std_logic;
 a0,a1,a2,a3                        : in   std_logic_vector(5 downto 0);
 s                                  : in   std_logic_vector(3 downto 0);
 --tsum                               : out  std_logic_vector(6 downto 0);
 weight                             : out  std_logic_vector(9 downto 0)
	);
END entity;

ARCHITECTURE rtl OF weight IS
component lpm_ad_sub IS
port
	(
		add_sub		: IN STD_LOGIC ;
		datab		  : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		result		 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
	);
END component;



component para_add IS
	PORT
	(
		data3x		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		data2x		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		data1x		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		data0x		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END component;

component acc IS
	PORT
	(
		dataa		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END component;

signal stemp                                      : std_logic_vector(3 downto 0);
signal start_temp0,start_temp1,start_temp2        : std_logic;
signal a0temp,a1temp,a2temp,a3temp                : std_logic_vector(5 downto 0);


signal sa0,sa1,sa2,sa3                : std_logic_vector(5 downto 0);
signal pa0,pa1,pa2,pa3                : std_logic_vector(5 downto 0);
signal psum                           : std_logic_vector(7 downto 0);
signal acc_a,acc_b,acc_sum            : std_logic_vector(9 downto 0);


begin

process(clk)
begin
  if clk'event and clk='1' then
     --stemp<=s;
     stemp<=not s;
     if a0(4)='1' then  a0temp<=a0; else a0temp<=a0+'1'; end if;
     if a1(4)='1' then  a1temp<=a1; else a1temp<=a1+'1'; end if;
     if a2(4)='1' then  a2temp<=a2; else a2temp<=a2+'1'; end if;
     if a3(4)='1' then  a3temp<=a3; else a3temp<=a3+'1'; end if;


     start_temp0<=start;
     start_temp1<=start_temp0;
     start_temp2<=start_temp1;
  end if;
end process;

lpm_ad_sub_inst0: lpm_ad_sub
port map
(
  stemp(0),  
  a0temp,
  sa0
  );
lpm_ad_sub_inst1: lpm_ad_sub
port map
(
  stemp(1),
  a1temp,
  sa1
  );
lpm_ad_sub_inst2: lpm_ad_sub
port map
(
  stemp(2),
  a2temp,
  sa2
  );
lpm_ad_sub_inst3: lpm_ad_sub
port map
(
  stemp(3),
  a3temp,
  sa3
  );


process(clk)
begin
   if clk'event and clk='1' then
      --ta0<=sa0;
      --ta1<=sa1;
      --ta2<=sa2;
      --ta3<=sa3;

      pa0<=sa0;
      pa1<=sa1;
      pa2<=sa2;
      pa3<=sa3;

   end if;
end process;

para_add_inst0: para_add
port map
(
 pa0,pa1,pa2,pa3,psum
);
process(clk)
begin
   if clk'event and clk='1' then
       --tsum<=psum;
       acc_b<= psum(7) & psum(7) & psum;
       case start_temp1 is
          when '1'=>acc_a<="0000000000";
          when '0'=>acc_a<=acc_sum;
       end case;
   end if;
end process;

acc_inst:acc
port map
(
  acc_a,acc_b,acc_sum
);

process(clk)
begin
   if clk'event and clk='1' then
     case start_temp1 is
         when '1'=>weight<=acc_sum;
         when '0'=>null;
     end case;
   end if;
   --tweight<=acc_sum;
end process;

end rtl;