datasel_tpc.vhd

来自「完整的TPC编译码VHDL程序」· VHDL 代码 · 共 44 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;

entity datasel_tpc is
port(
		reset	:in		std_logic;
		mclk	:in		std_logic;
		datai_in	:in		std_logic_vector(11 downto 0);
		dataq_in	:in		std_logic_vector(11 downto 0);			
		datai_out	:out	std_logic_vector(4 downto 0);			
		dataq_out	:out	std_logic_vector(4 downto 0)			
				
	);
end datasel_tpc;

architecture arch of datasel_tpc is 

begin
process(reset,mclk)
begin
if reset='0' then
	datai_out<=conv_std_logic_vector(0,5);	
	dataq_out<=conv_std_logic_vector(0,5);		
elsif mclk 'event and mclk='1' then
	if datai_in>conv_std_logic_vector(127,12) then
		datai_out<=conv_std_logic_vector(15,5);
	elsif datai_in<conv_std_logic_vector(-128,12) then
		datai_out<=conv_std_logic_vector(-16,5);	
	else
		datai_out<=datai_in(7 downto 3);
	end if;
	if dataq_in>conv_std_logic_vector(127,12) then
		dataq_out<=conv_std_logic_vector(15,5);
	elsif dataq_in<conv_std_logic_vector(-128,12) then
		dataq_out<=conv_std_logic_vector(-16,5);	
	else
		dataq_out<=dataq_in(7 downto 3);
	end if;
end if;
end process;

end arch;