div.vhd

完整的TPC编译码VHDL程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY div IS
	PORT
	(
		clk		                               : in  std_logic;
  rowbegin                            : in  std_logic;
  rowend                              : in  std_logic;
  sq0,sq1,sq2,sq3,sq4,sq5             : in  std_logic_vector(3 downto 0);
  sq6,sq7,sq8,sq9,sq10                : in  std_logic_vector(3 downto 0);
  sq11,sq12,sq13,sq14,sq15            : in  std_logic_vector(3 downto 0);

  sy0,sy1,sy2,sy3,sy4,sy5             : out std_logic_vector(4 downto 0);
  sy6,sy7,sy8,sy9,sy10                : out std_logic_vector(4 downto 0);
  sy11,sy12,sy13,sy14,sy15            : out std_logic_vector(4 downto 0);

  pr0,pr1,pr2,pr3,pr4,pr5             : out std_logic;
  pr6,pr7,pr8,pr9,pr10                : out std_logic;
  pr11,pr12,pr13,pr14,pr15            : out std_logic

	);
END entity;

ARCHITECTURE rtl OF div IS

component g_div IS
PORT
(
  clk		                              : in  std_logic;
  row_firb                           : in  std_logic;
  row_end                            : in  std_logic;
  seq                                : in  std_logic_vector(3 downto 0);
  synd                               : out std_logic_vector(4 downto 0);
  parity                             : out  std_logic
	);
END component;
begin

gdiv_inst0: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq0,                                
  sy0,
  pr0                              
	);
gdiv_inst1: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq1,                                
  sy1,
  pr1                               
);
gdiv_inst2: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq2,                                
  sy2,
  pr2                               
	);
gdiv_inst3: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq3,                                
  sy3,
  pr3                               
	);
gdiv_inst4: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq4,                                
  sy4,
  pr4                               
	);
gdiv_inst5: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq5,                                
  sy5,
  pr5                               
	);
gdiv_inst6: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq6,                                
  sy6,
  pr6                                 
	);
gdiv_inst7: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq7,                                
  sy7,
  pr7                                
	);
gdiv_inst8: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq8,                                
  sy8,
  pr8                                 
	);
gdiv_inst9: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq9,                                
  sy9,
  pr9                                
	);
gdiv_inst10: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq10,                                
  sy10,
  pr10                               
	);
gdiv_inst11: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq11,                                
  sy11,
  pr11                               
	);
gdiv_inst12: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq12,                                
  sy12,
  pr12                                
	);
gdiv_inst13: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq13,                                
  sy13,
  pr13                                
	);
gdiv_inst14: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq14,                                
  sy14,
  pr14                               
	);
gdiv_inst15: g_div 
	PORT MAP
	(
		clk,		                              
  rowbegin,
  rowend, 
  sq15,                                
  sy15,
  pr15                               
	);


end rtl;