shift.vhd

完整的TPC编译码VHDL程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.std_logic_arith.all;
ENTITY shift IS
   PORT( clk              : in std_logic;
         input            : in std_logic;
         output           : out std_logic 
	   );
END  shift;

ARCHITECTURE rtl OF shift IS
signal shift0,shift1,shift2,shift3,shift4              : std_logic;
signal shift5,shift6,shift7,shift8,shift9              : std_logic;

begin

process(clk)
begin
    if clk'event and clk='1' then
       shift0<=input;
       shift1<=shift0;
       shift2<=shift1;
       shift3<=shift2;
       shift4<=shift3;
       shift5<=shift4;
       shift6<=shift5;
       shift7<=shift6;
       shift8<=shift7;
       output<=shift8;
    end if;
end process;



end rtl;