fj.vhd

完整的TPC编译码VHDL程序

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity fj is
    port(clk                  : in  std_logic;
         data_in              : in  std_logic;
         clkx2                : in  std_logic;
         fjena                : in  std_logic;
         encback              : in  std_logic;
         power_ctrldata       : in  std_logic;   
         

         t_dout               : out std_logic_vector(0 downto 0);
         tcount1              : out std_logic_vector(8 downto 0);
         twr                  : out std_logic_vector(9 downto 0);
         tcount2              : out std_logic_vector(8 downto 0);
         th                   : out std_logic;
         t_full               : out std_logic;
         t_col                : out std_logic;
         t_count3             : out std_logic_vector(4 downto 0);
         t_count4             : out std_logic_vector(8 downto 0);
         t_preamble           : out std_logic;
         t_data_en            : out std_logic;
         t_count5             : out std_logic_vector(8 downto 0);
         t_turn               : out std_logic;
         t_raddr              : out std_logic_vector(9 downto 0);
         t_rom_dout           : out std_logic_vector(0 downto 0);
         fjout                : out std_logic;
         test_fjout           : out std_logic_vector(0 downto 0);
         test_encout          : out std_logic_vector(0 downto 0);
         tfr_head,mapflag     : out std_logic; 
         t_ram                : out std_logic_vector(0 downto 0)
);
end fj;
architecture arch of fj is
signal ena_temp0,ena_temp1   :  std_logic;
signal fjenat0   :  std_logic;

signal din0,din1                              :  std_logic;
signal dtemp                                :  std_logic_vector(0 downto 0);
signal count1                               :  std_logic_vector(8 downto 0);
signal waddr                                :  std_logic_vector(9 downto 0);
signal raddr                                :  std_logic_vector(9 downto 0);
signal highbit                              :  std_logic;
signal r_highbit0,r_highbit1,r_highbit2               :  std_logic;

signal count2                               :  std_logic_vector(8 downto 0);
signal count2ena,full                       :  std_logic;
signal c2enat0,c2enat1,c2enat2                       :  std_logic;
signal c2enat3,c2enat4,c2enat5                       :  std_logic;

signal preamble                             :  std_logic;
signal data_en                              :  std_logic;
signal col_check                            :  std_logic;
signal count3                               :  std_logic_vector(4 downto 0);
signal count4                               :  std_logic_vector(8 downto 0);
signal dataentemp0,dataentemp1,dataentemp2     :  std_logic;
signal dataentemp3,dataentemp4,dataentemp5     :  std_logic;
signal dataentemp6,dataentemp7,dataentemp8     :  std_logic;
signal dataentemp9,dataentemp10,dataentemp11   :  std_logic;
signal dataentemp12,dataentemp13,dataentemp14  :  std_logic;
signal dataentemp15,dataentemp16               :  std_logic;

signal count2temp0,count2temp1,count2temp2  :  std_logic_vector(8 downto 0);

signal preamble_temp0,preamble_temp1,preamble_temp2 : std_logic;
signal preamble_temp3,preamble_temp4,preamble_temp5 : std_logic;
signal preamble_temp6,preamble_temp7,preamble_temp8 : std_logic;


signal ramturn,ramturnt0                             :  std_logic;
signal dout,dout_temp                      :  std_logic_vector(0 downto 0);
signal rom_dout,rom_dout_temp              :  std_logic_vector(0 downto 0);

signal fjout_temp                            :  std_logic_vector(0 downto 0);
signal raddr_temp0,raddr_temp1,raddr_temp2   :  std_logic_vector(9 downto 0);
signal raddr_temp3,raddr_temp4,raddr_temp5   :  std_logic_vector(9 downto 0);
signal raddr_temp6,raddr_temp7,raddr_temp8   :  std_logic_vector(9 downto 0);
signal raddr_temp9,raddr_temp10,raddr_temp11 :  std_logic_vector(9 downto 0);
signal raddr_temp12,raddr_temp13             :  std_logic_vector(9 downto 0);

signal encback_temp                          :  std_logic_vector(0 downto 0); 

signal fr_head                               :  std_logic;
signal frh_t0,frh_t1,frh_t2,frh_t3,frh_t4    :  std_logic;
signal frh_t5,frh_t6,frh_t7,frh_t8,frh_t9    :  std_logic;
signal frh_t10,frh_t11,frh_t12,frh_t13,frh_t14    :  std_logic;
signal frhflag                   :  std_logic_vector(1 downto 0);
signal fmap0,fmap1,fmap2,fmap3,fmap4,fmap5,fmap6    :  std_logic;
signal power_ctrldata_temp       :  std_logic_vector(0 downto 0);
signal powerctrl,powerctrl_temp0      :  std_logic;
signal powerctrl_temp1,powerctrl_temp2,powerctrl_temp3      :  std_logic;
signal powerctrl_temp4,powerctrl_temp5,powerctrl_temp6      :  std_logic;
component fjram IS
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		wraddress		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		rden		: IN STD_LOGIC  := '1';
		wrclock		: IN STD_LOGIC ;
		rdclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
	);
END component;



component prom IS
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
	);
END component;

component fjena_shift IS
   PORT(clk              : in std_logic;
        input           : in std_logic;
        output          : out std_logic
	   );
END  component;

component fjturn_shift IS
   PORT(clk              : in std_logic;
        input           : in std_logic;
        output          : out std_logic
	   );
END  component;

component mapena_shift IS
   PORT(clk              : in std_logic;
        input           : in std_logic;
        output          : out std_logic
	   );
END  component;


begin

process(fjena)
begin
   if fjena'event and fjena='1' then
       power_ctrldata_temp(0)<=power_ctrldata;
   end if;
end process;



process(clk)
begin
   if clk'event and clk='1' then
     if fjena='1' then
       count1<="100011011";
     else
      case count1 is
         when "100011011"=>count1<="000011100";
         when others=>count1<=count1+"000000001";
      end case;
    end if;
      din0<=data_in;
      dtemp(0)<=din0;
    end if;
end process;

process(clk)
begin
    if clk'event and clk='1' then
      case count1 is
         when "100011011"=>highbit<=not highbit;
         when others=>null;
      end case;
      waddr<=highbit & count1;
      twr<=waddr;
      tcount1<=count1;
      th<=highbit;
      r_highbit0<=highbit;
      r_highbit1<=r_highbit0;
      r_highbit2<=r_highbit1;

    end if;
end process;

process(clk)
begin
if clk'event and clk='1' then
    t_dout<=dtemp;--dout_temp;
    t_ram<=dout_temp;
end if;
end process;


fjram_inst : fjram PORT MAP (
		data	 => dtemp,
		wren	 => '1',
		wraddress	 => waddr,
		rdaddress	 => raddr,
		rden	 => '1',
		wrclock	 => clk,
		rdclock	 => clkx2,
		q	 => dout
	);

prom_inst : prom PORT MAP (
		address	 => raddr(4 downto 0),
		clock	 => clkx2,
		q	 => rom_dout
	);
	
	
fjenasft: fjena_shift    PORT map(clk,fjena,fjenat0);
ena_sft0: mapena_shift   port map(clk,fjenat0,fmap0);
ramturnsft:fjturn_shift  PORT map(clk,r_highbit2,ramturnt0);



process(clk)
begin
  if clk'event and clk='1' then
      case count1 is
        when "100011011" =>full<='1';
        when others=>full<='0'; 
      end case;
      t_full<=fjenat0;
  end if;
end process;

count2ena<=fjenat0 and clk;

process(clkx2)
begin
   if clkx2'event and clkx2='1' then
       c2enat0<=count2ena;
       c2enat1<=c2enat0;
       c2enat2<=c2enat1;
       c2enat3<=c2enat2;
       c2enat4<=c2enat3;

       ramturn<=ramturnt0;
    end if;
end process;

process(clkx2)
begin
  if clkx2'event and clkx2='1' then
     if count2ena='1' then
             count2<="111111111";
     else
        case count2 is
          when "111111111"=>count2<="000000000";
          when others=>count2<=count2+"000000001";
        end case;
      end if;
  end if;
end process;


process(clkx2)
begin
  if clkx2'event and clkx2='1' then
     tcount2<=count2temp2;
  end if;
end process;

process(clkx2)
begin
if clkx2'event and clkx2='1' then
  case count2 is
      when "111111111"=>preamble<='1';
      when "000011011"=>preamble<='0';
      when others=>null;
  end case;
 end if;
end process;

process(clkx2)
begin
if clkx2'event and clkx2='1' then
  case count2 is
      when "000010101"=>powerctrl<='1';
      when "000011011"=>powerctrl<='0';
      when others=>null;
  end case;
 end if;
end process;


process(clkx2)
begin
  if clkx2'event and clkx2='1' then
   case  count2 is
      when "101111100"=>col_check<='0';---???????279 or 280
      when "111111111"=>col_check<='1';
      when others=>null;
   end case;
  end if;
end process;

process(clkx2)
begin
   if  clkx2'event and clkx2='1' then
      if preamble='1' then
        count3<="10101";
      else
        case count3 is
          when "10101"=>count3<="00000";
          when others=> count3<=count3+"00001";
        end case;
      end if;
  end if;
end process;

process(clkx2)
begin
  if clkx2'event and clkx2='1' then
    if preamble='1' then
        data_en<='0';
    elsif preamble='0' then
        case count3 is
          when "10101"=>data_en<='1';
          when "01111"=>data_en<='0';
          when others=>null;
       end case;
    end if;
 end if;
end process;

process(clkx2)
begin
if clkx2'event and clkx2='1' then
     dataentemp0<=data_en and col_check;
end if;
end process;


process(clkx2)
begin
if clkx2'event and clkx2='1' then
  if preamble_temp1='1' then
     count4<="000011011";
  else
     if dataentemp0='1' then
        count4<=count4+"000000001";
     end if;
  end if;
end if;
end process;

process(clkx2)
begin
if clkx2'event and clkx2='1' then
   count2temp0<=count2;
   count2temp1<=count2temp0;
   count2temp2<=count2temp1;
  
   preamble_temp0<=preamble;
   preamble_temp1<=preamble_temp0;
   preamble_temp2<=preamble_temp1;
   preamble_temp3<=preamble_temp2;
   preamble_temp4<=preamble_temp3;
   preamble_temp5<=preamble_temp4;
   preamble_temp6<=preamble_temp5;
   preamble_temp7<=preamble_temp6;

   powerctrl_temp0<=powerctrl;
   powerctrl_temp1<=powerctrl_temp0;
   powerctrl_temp2<=powerctrl_temp1;
   powerctrl_temp3<=powerctrl_temp2;
   powerctrl_temp4<=powerctrl_temp3;
   powerctrl_temp5<=powerctrl_temp4;
   powerctrl_temp6<=powerctrl_temp5;


   dataentemp1<=dataentemp0;
   dataentemp2<=dataentemp1;
   dataentemp3<=dataentemp2;
   dataentemp4<=dataentemp3;
   dataentemp5<=dataentemp4;
   dataentemp6<=dataentemp5;
   dataentemp7<=dataentemp6;
   dataentemp8<=dataentemp7;
   dataentemp9<=dataentemp8;
   dataentemp10<=dataentemp9;
   dataentemp11<=dataentemp10;
   dataentemp12<=dataentemp11;
   dataentemp13<=dataentemp12;
   dataentemp14<=dataentemp13;
   dataentemp15<=dataentemp14;
   dataentemp16<=dataentemp15;

   --ramturn<=r_highbit1;

end if;
end process;

process(clkx2)
begin
if clkx2'event and clkx2='1' then
   case  preamble_temp2 is
      when '1'=>raddr<=ramturn & count2temp2;
      when '0'=>raddr<=ramturn & count4;
   end case;
end if;
end process;

process(clkx2)
begin
if clkx2'event and clkx2='1' then
   case  count2 is
      when "000000000"=>fr_head<='1';
      when others=>fr_head<='0';
   end case;
   frh_t0<=fr_head;
   frh_t1<=frh_t0;
   frh_t2<=frh_t1;
   frh_t3<=frh_t2;
   frh_t4<=frh_t3;
   frh_t5<=frh_t4;
   frh_t6<=frh_t5;
   frh_t7<=frh_t6;
   frh_t8<=frh_t7;
   frh_t9<=frh_t8;
   frh_t10<=frh_t9;
   frh_t11<=frh_t10;
   frh_t12<=frh_t11;

   tfr_head<=frh_t12;
   
end if;
end process;
   


process(clk)
begin
if clk'event and clk='1' then
   --fmap0<=fjenat0;
   fmap1<=fmap0;
   fmap2<=fmap1;
   fmap3<=fmap2;
   fmap4<=fmap3;
   fmap5<=fmap4;

   mapflag<=fmap0;
end if;
end process;



process(clkx2)
begin
if clkx2'event and clkx2='1' then
   case  preamble_temp5 is
      when '1'=>dout_temp<="Z";
                rom_dout_temp<=rom_dout;
      when '0'=>dout_temp<=dout;
                rom_dout_temp<="Z";
   end case;
end if;
end process;

process(clkx2)
begin
if clkx2'event and clkx2='1' then
   case  preamble_temp6 is
      when '1'=>case powerctrl_temp6 is
                    when '0'=>fjout_temp<=rom_dout_temp;
                    when '1'=>fjout_temp<=power_ctrldata_temp;
                end case;
      when '0'=>fjout_temp<=dout_temp;
   end case;
end if;
end process;

process(clkx2)
begin
if clkx2'event and clkx2='1' then
   fjout<=fjout_temp(0);
end if;
end process;


--==========================================
process(clkx2)
begin
  if clkx2'event and clkx2='1' then
     raddr_temp0<=raddr;
     raddr_temp1<=raddr_temp0;
     raddr_temp2<=raddr_temp1;
     raddr_temp3<=raddr_temp2;
     raddr_temp4<=raddr_temp3;
     raddr_temp5<=raddr_temp4;
     raddr_temp6<=raddr_temp5;
     raddr_temp7<=raddr_temp6;
     raddr_temp8<=raddr_temp7;
     raddr_temp9<=raddr_temp8;
     raddr_temp10<=raddr_temp9;
     raddr_temp11<=raddr_temp10;
     raddr_temp12<=raddr_temp11;
     raddr_temp13<=raddr_temp12;

  end if;
end process;
fjram_inst1 : fjram PORT MAP (
		data	 => fjout_temp,
		wren	 => '1',
		wraddress	 => raddr_temp3,
		rdaddress	 => waddr,
		rden	 => '1',
		wrclock	 =>clkx2,
		rdclock	 =>clk,
		q	 => test_fjout
	);

process(clkx2)
begin
if clkx2'event and clkx2='1' then
   encback_temp(0)<=encback;
end if;
end process;

fjram_inst2 : fjram PORT MAP (
		data	 => encback_temp,
		wren	 => dataentemp16,
		wraddress	 =>raddr_temp13,
		rdaddress	 => waddr,
		rden	 => '1',
		wrclock	 =>clkx2,
		rdclock	 =>clk,
		q	 => test_encout
	);

process(clkx2)
begin
if clkx2'event and clkx2='1' then
    t_col<=col_check;
    t_count3<=count3;
    t_count4<=count4;
    t_count5<=count2temp2;

    t_preamble<=preamble_temp7;
    t_data_en<=dataentemp6;
    t_turn<=ramturn;
    t_raddr<=raddr;--_temp11;
    --t_dout<=dtemp;--dout_temp;
    t_rom_dout<=rom_dout_temp;
end if;
end process;



end arch;