encoder.vhd

完整的TPC编译码VHDL程序

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY encoder IS 
	port
	(
		dinclk :  IN  STD_LOGIC;
		dain :  IN  STD_LOGIC;
		encclk :  IN  STD_LOGIC;
		datainena :  IN  STD_LOGIC;
		power_ctl :  IN  STD_LOGIC;
		fjmapflag :  OUT  STD_LOGIC;
		Iout :  OUT  STD_LOGIC;
		Qout :  OUT  STD_LOGIC;
		mapclk :  OUT  STD_LOGIC;
		tencout :  OUT  STD_LOGIC;
		Isym :  OUT  STD_LOGIC_VECTOR(4 downto 0);
		Qsym :  OUT  STD_LOGIC_VECTOR(4 downto 0)
	);
END encoder;

ARCHITECTURE bdf_type OF encoder IS 

component fj
	PORT(clk : IN STD_LOGIC;
		 data_in : IN STD_LOGIC;
		 clkx2 : IN STD_LOGIC;
		 fjena : IN STD_LOGIC;
		 encback : IN STD_LOGIC;
		 power_ctrldata : IN STD_LOGIC;
		 th : OUT STD_LOGIC;
		 t_full : OUT STD_LOGIC;
		 t_col : OUT STD_LOGIC;
		 t_preamble : OUT STD_LOGIC;
		 t_data_en : OUT STD_LOGIC;
		 t_turn : OUT STD_LOGIC;
		 fjout : OUT STD_LOGIC;
		 tfr_head : OUT STD_LOGIC;
		 mapflag : OUT STD_LOGIC;
		 t_count3 : OUT STD_LOGIC_VECTOR(4 downto 0);
		 t_count4 : OUT STD_LOGIC_VECTOR(8 downto 0);
		 t_count5 : OUT STD_LOGIC_VECTOR(8 downto 0);
		 t_dout : OUT STD_LOGIC_VECTOR(0 to 0);
		 t_raddr : OUT STD_LOGIC_VECTOR(9 downto 0);
		 t_ram : OUT STD_LOGIC_VECTOR(0 to 0);
		 t_rom_dout : OUT STD_LOGIC_VECTOR(0 to 0);
		 tcount1 : OUT STD_LOGIC_VECTOR(8 downto 0);
		 tcount2 : OUT STD_LOGIC_VECTOR(8 downto 0);
		 test_encout : OUT STD_LOGIC_VECTOR(0 to 0);
		 test_fjout : OUT STD_LOGIC_VECTOR(0 to 0);
		 twr : OUT STD_LOGIC_VECTOR(9 downto 0)
	);
end component;

component enc32
	PORT(data_in : IN STD_LOGIC;
		 enclk : IN STD_LOGIC;
		 uniquebit : IN STD_LOGIC;
		 den : IN STD_LOGIC;
		 t_data_in : OUT STD_LOGIC;
		 t_data0 : OUT STD_LOGIC;
		 t_buf_we : OUT STD_LOGIC;
		 t_buf_rden : OUT STD_LOGIC;
		 tuniquebit : OUT STD_LOGIC;
		 t_rpar : OUT STD_LOGIC;
		 t_xencout : OUT STD_LOGIC;
		 t_xdata0 : OUT STD_LOGIC;
		 t_ydata0 : OUT STD_LOGIC;
		 t_uniquebit_temp : OUT STD_LOGIC;
		 t_encout : OUT STD_LOGIC;
		 t_buf_din : OUT STD_LOGIC_VECTOR(5 downto 0);
		 t_bufq : OUT STD_LOGIC_VECTOR(5 downto 0);
		 t_bufwad : OUT STD_LOGIC_VECTOR(4 downto 0);
		 t_count1 : OUT STD_LOGIC_VECTOR(4 downto 0);
		 t_count2 : OUT STD_LOGIC_VECTOR(4 downto 0);
		 t_count3 : OUT STD_LOGIC_VECTOR(4 downto 0);
		 t_count4 : OUT STD_LOGIC_VECTOR(4 downto 0);
		 t_raddr : OUT STD_LOGIC_VECTOR(4 downto 0);
		 t_reg : OUT STD_LOGIC_VECTOR(4 downto 0)
	);
end component;

component qpsk_map
	PORT(clk : IN STD_LOGIC;
		 clk2x : IN STD_LOGIC;
		 flag : IN STD_LOGIC;
		 encoded : IN STD_LOGIC_VECTOR(0 to 0);
		 iout : OUT STD_LOGIC;
		 qout : OUT STD_LOGIC;
		 encin : OUT STD_LOGIC_VECTOR(0 to 0);
		 isym : OUT STD_LOGIC_VECTOR(4 downto 0);
		 qsym : OUT STD_LOGIC_VECTOR(4 downto 0);
		 tcnt1 : OUT STD_LOGIC_VECTOR(2 downto 0);
		 tcnt2 : OUT STD_LOGIC_VECTOR(1 downto 0)
	);
end component;

signal	encout :  STD_LOGIC;
signal	fj2enc :  STD_LOGIC;
signal	fj_den :  STD_LOGIC;
signal	fj_mapflag :  STD_LOGIC;
signal	fj_preamble :  STD_LOGIC;
signal	fjhead :  STD_LOGIC;
signal	tencfb :  STD_LOGIC_VECTOR(0 to 0);


BEGIN 
mapclk <= dinclk;



b2v_inst : fj
PORT MAP(clk => dinclk,
		 data_in => dain,
		 clkx2 => encclk,
		 fjena => datainena,
		 encback => encout,
		 power_ctrldata => power_ctl,
		 t_preamble => fj_preamble,
		 t_data_en => fj_den,
		 fjout => fj2enc,
		 tfr_head => fjhead,
		 mapflag => fj_mapflag,
		 test_encout => tencfb);

b2v_inst1 : enc32
PORT MAP(data_in => fj2enc,
		 enclk => encclk,
		 uniquebit => fj_preamble,
		 den => fj_den,
		 t_encout => encout);

b2v_inst2 : qpsk_map
PORT MAP(clk => dinclk,
		 clk2x => encclk,
		 flag => fjhead,
		 encoded(0) => encout,
		 iout => Iout,
		 qout => Qout,
		 isym => Isym,
		 qsym => Qsym);
fjmapflag <= fj_mapflag;
tencout <= tencfb(0);

END;