alu.hier_info

verilog hdl经典例程

|alu
out[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
out[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
opcode[0] => Mux7.IN10
opcode[0] => Mux6.IN10
opcode[0] => Mux5.IN10
opcode[0] => Mux4.IN10
opcode[0] => Mux3.IN10
opcode[0] => Mux2.IN10
opcode[0] => Mux1.IN10
opcode[0] => Mux0.IN10
opcode[1] => Mux7.IN9
opcode[1] => Mux6.IN9
opcode[1] => Mux5.IN9
opcode[1] => Mux4.IN9
opcode[1] => Mux3.IN9
opcode[1] => Mux2.IN9
opcode[1] => Mux1.IN9
opcode[1] => Mux0.IN9
opcode[2] => Mux7.IN8
opcode[2] => Mux6.IN8
opcode[2] => Mux5.IN8
opcode[2] => Mux4.IN8
opcode[2] => Mux3.IN8
opcode[2] => Mux2.IN8
opcode[2] => Mux1.IN8
opcode[2] => Mux0.IN8
a[0] => out~8.IN0
a[0] => out~0.IN0
a[0] => Add1.IN16
a[0] => Add0.IN8
a[0] => Mux7.IN7
a[1] => out~9.IN0
a[1] => out~1.IN0
a[1] => Add1.IN15
a[1] => Add0.IN7
a[1] => Mux6.IN7
a[2] => out~10.IN0
a[2] => out~2.IN0
a[2] => Add1.IN14
a[2] => Add0.IN6
a[2] => Mux5.IN7
a[3] => out~11.IN0
a[3] => out~3.IN0
a[3] => Add1.IN13
a[3] => Add0.IN5
a[3] => Mux4.IN7
a[4] => out~12.IN0
a[4] => out~4.IN0
a[4] => Add1.IN12
a[4] => Add0.IN4
a[4] => Mux3.IN7
a[5] => out~13.IN0
a[5] => out~5.IN0
a[5] => Add1.IN11
a[5] => Add0.IN3
a[5] => Mux2.IN7
a[6] => out~14.IN0
a[6] => out~6.IN0
a[6] => Add1.IN10
a[6] => Add0.IN2
a[6] => Mux1.IN7
a[7] => out~15.IN0
a[7] => out~7.IN0
a[7] => Add1.IN9
a[7] => Add0.IN1
a[7] => Mux0.IN7
b[0] => out~8.IN1
b[0] => out~0.IN1
b[0] => Add0.IN16
b[0] => Add1.IN8
b[1] => out~9.IN1
b[1] => out~1.IN1
b[1] => Add0.IN15
b[1] => Add1.IN7
b[2] => out~10.IN1
b[2] => out~2.IN1
b[2] => Add0.IN14
b[2] => Add1.IN6
b[3] => out~11.IN1
b[3] => out~3.IN1
b[3] => Add0.IN13
b[3] => Add1.IN5
b[4] => out~12.IN1
b[4] => out~4.IN1
b[4] => Add0.IN12
b[4] => Add1.IN4
b[5] => out~13.IN1
b[5] => out~5.IN1
b[5] => Add0.IN11
b[5] => Add1.IN3
b[6] => out~14.IN1
b[6] => out~6.IN1
b[6] => Add0.IN10
b[6] => Add1.IN2
b[7] => out~15.IN1
b[7] => out~7.IN1
b[7] => Add0.IN9
b[7] => Add1.IN1