sort4.hier_info

verilog hdl经典例程

|sort4
ra[0] <= x~11.DB_MAX_OUTPUT_PORT_TYPE
ra[1] <= x~10.DB_MAX_OUTPUT_PORT_TYPE
ra[2] <= x~9.DB_MAX_OUTPUT_PORT_TYPE
ra[3] <= x~8.DB_MAX_OUTPUT_PORT_TYPE
rb[0] <= y~11.DB_MAX_OUTPUT_PORT_TYPE
rb[1] <= y~10.DB_MAX_OUTPUT_PORT_TYPE
rb[2] <= y~9.DB_MAX_OUTPUT_PORT_TYPE
rb[3] <= y~8.DB_MAX_OUTPUT_PORT_TYPE
rc[0] <= x~15.DB_MAX_OUTPUT_PORT_TYPE
rc[1] <= x~14.DB_MAX_OUTPUT_PORT_TYPE
rc[2] <= x~13.DB_MAX_OUTPUT_PORT_TYPE
rc[3] <= x~12.DB_MAX_OUTPUT_PORT_TYPE
rd[0] <= y~15.DB_MAX_OUTPUT_PORT_TYPE
rd[1] <= y~14.DB_MAX_OUTPUT_PORT_TYPE
rd[2] <= y~13.DB_MAX_OUTPUT_PORT_TYPE
rd[3] <= y~12.DB_MAX_OUTPUT_PORT_TYPE
a[0] => y~3.DATAB
a[0] => x~3.DATAA
a[0] => LessThan0.IN4
a[1] => y~2.DATAB
a[1] => x~2.DATAA
a[1] => LessThan0.IN3
a[2] => y~1.DATAB
a[2] => x~1.DATAA
a[2] => LessThan0.IN2
a[3] => y~0.DATAB
a[3] => x~0.DATAA
a[3] => LessThan0.IN1
b[0] => y~7.DATAB
b[0] => x~7.DATAA
b[0] => LessThan1.IN4
b[1] => y~6.DATAB
b[1] => x~6.DATAA
b[1] => LessThan1.IN3
b[2] => y~5.DATAB
b[2] => x~5.DATAA
b[2] => LessThan1.IN2
b[3] => y~4.DATAB
b[3] => x~4.DATAA
b[3] => LessThan1.IN1
c[0] => y~3.DATAA
c[0] => x~3.DATAB
c[0] => LessThan0.IN8
c[1] => y~2.DATAA
c[1] => x~2.DATAB
c[1] => LessThan0.IN7
c[2] => y~1.DATAA
c[2] => x~1.DATAB
c[2] => LessThan0.IN6
c[3] => y~0.DATAA
c[3] => x~0.DATAB
c[3] => LessThan0.IN5
d[0] => y~7.DATAA
d[0] => x~7.DATAB
d[0] => LessThan1.IN8
d[1] => y~6.DATAA
d[1] => x~6.DATAB
d[1] => LessThan1.IN7
d[2] => y~5.DATAA
d[2] => x~5.DATAB
d[2] => LessThan1.IN6
d[3] => y~4.DATAA
d[3] => x~4.DATAB
d[3] => LessThan1.IN5