p_to_s.v

来自「verilog hdl经典例程」· Verilog 代码 · 共 19 行

module p_to_s(D_in,T0,data,SEND,ESC,ADD_100);
output D_in,T0;
input [7:0] data;
input SEND,ESC,ADD_100;
wire D_in,T0;
reg [7:0] DATA_Q,DATA_Q_buf;
assign T0=!(SEND&ESC);
assign D_in=DATA_Q[7];
always @(posedge T0 or negedge ADD_100)
begin
  if(!ADD_100)
  DATA_Q=data;
  else
  begin
  DATA_Q_buf=DATA_Q<<1;
  DATA_Q=DATA_Q_buf;
  end
  end
  endmodule