comparetop.v

verilog hdl经典例程

module compareTop;
wire [3:0] b1,c1,b2,c2;
reg [3:0] a;
reg clk;
initial
begin
clk=0;
forever #50 clk=~clk;
end
initial
begin
a=4'h3;
$display("______________________");
# 100 a=4'h7;
$dispaly("______________________");
# 100 a=4'hf;
$dispaly("______________________");
#100 a=4'ha;
$dispaly("_______________________");
# 100 a=4'h2;
$display("_______________________");
$stop;
end
non_blocking non_blocking(clk,a,b2,c2);
blocking blocking(clk,a,b1,c1);
endmodule