at91rm9200.h

ARM板驱动程序源代码

/* ******************************************************************************/
typedef struct _AT91S_AIC {
	AT91_REG	 AIC_SMR[32]; 	/* Source Mode Register*/
	AT91_REG	 AIC_SVR[32]; 	/* Source Vector Register*/
	AT91_REG	 AIC_IVR; 	/* IRQ Vector Register*/
	AT91_REG	 AIC_FVR; 	/* FIQ Vector Register*/
	AT91_REG	 AIC_ISR; 	/* Interrupt Status Register*/
	AT91_REG	 AIC_IPR; 	/* Interrupt Pending Register*/
	AT91_REG	 AIC_IMR; 	/* Interrupt Mask Register*/
	AT91_REG	 AIC_CISR; 	/* Core Interrupt Status Register*/
	AT91_REG	 Reserved0[2]; 	/* */
	AT91_REG	 AIC_IECR; 	/* Interrupt Enable Command Register*/
	AT91_REG	 AIC_IDCR; 	/* Interrupt Disable Command Register*/
	AT91_REG	 AIC_ICCR; 	/* Interrupt Clear Command Register*/
	AT91_REG	 AIC_ISCR; 	/* Interrupt Set Command Register*/
	AT91_REG	 AIC_EOICR; 	/* End of Interrupt Command Register*/
	AT91_REG	 AIC_SPU; 	/* Spurious Vector Register*/
	AT91_REG	 AIC_DCR; 	/* Debug Control Register (Protect)*/
	AT91_REG	 Reserved1[1]; 	/* */
	AT91_REG	 AIC_FFER; 	/* Fast Forcing Enable Register*/
	AT91_REG	 AIC_FFDR; 	/* Fast Forcing Disable Register*/
	AT91_REG	 AIC_FFSR; 	/* Fast Forcing Status Register*/
} AT91S_AIC, *AT91PS_AIC;

/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) /* (AIC) Priority Level*/
#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) /* (AIC) Lowest priority level*/
#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) /* (AIC) Highest priority level*/
#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) /* (AIC) Interrupt Source Type*/
#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  ((unsigned int) 0x0 <<  5) /* (AIC) Internal Sources Code Label Level Sensitive*/
#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   ((unsigned int) 0x1 <<  5) /* (AIC) Internal Sources Code Label Edge triggered*/
#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       ((unsigned int) 0x2 <<  5) /* (AIC) External Sources Code Label High-level Sensitive*/
#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    ((unsigned int) 0x3 <<  5) /* (AIC) External Sources Code Label Positive Edge triggered*/
/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) /* (AIC) NFIQ Status*/
#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) /* (AIC) NIRQ Status*/
/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) /* (AIC) Protection Mode*/
#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) /* (AIC) General Mask*/

/* ******************************************************************************/
/*              SOFTWARE API DEFINITION  FOR Serial Parallel Interface*/
/* ******************************************************************************/
typedef struct _AT91S_SPI {
	AT91_REG	 SPI_CR; 	/* Control Register*/
	AT91_REG	 SPI_MR; 	/* Mode Register*/
	AT91_REG	 SPI_RDR; 	/* Receive Data Register*/
	AT91_REG	 SPI_TDR; 	/* Transmit Data Register*/
	AT91_REG	 SPI_SR; 	/* Status Register*/
	AT91_REG	 SPI_IER; 	/* Interrupt Enable Register*/
	AT91_REG	 SPI_IDR; 	/* Interrupt Disable Register*/
	AT91_REG	 SPI_IMR; 	/* Interrupt Mask Register*/
	AT91_REG	 Reserved0[4]; 	/* */
	AT91_REG	 SPI_CSR[4]; 	/* Chip Select Register*/
	AT91_REG	 Reserved1[48]; 	/* */
	AT91_REG	 SPI_RPR; 	/* Receive Pointer Register*/
	AT91_REG	 SPI_RCR; 	/* Receive Counter Register*/
	AT91_REG	 SPI_TPR; 	/* Transmit Pointer Register*/
	AT91_REG	 SPI_TCR; 	/* Transmit Counter Register*/
	AT91_REG	 SPI_RNPR; 	/* Receive Next Pointer Register*/
	AT91_REG	 SPI_RNCR; 	/* Receive Next Counter Register*/
	AT91_REG	 SPI_TNPR; 	/* Transmit Next Pointer Register*/
	AT91_REG	 SPI_TNCR; 	/* Transmit Next Counter Register*/
	AT91_REG	 SPI_PTCR; 	/* PDC Transfer Control Register*/
	AT91_REG	 SPI_PTSR; 	/* PDC Transfer Status Register*/
} AT91S_SPI, *AT91PS_SPI;

/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) /* (SPI) SPI Enable*/
#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) /* (SPI) SPI Disable*/
#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) /* (SPI) SPI Software reset*/
/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) /* (SPI) Master/Slave Mode*/
#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) /* (SPI) Peripheral Select*/
#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) /* (SPI) Fixed Peripheral Select*/
#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) /* (SPI) Variable Peripheral Select*/
#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) /* (SPI) Chip Select Decode*/
#define AT91C_SPI_DIV32       ((unsigned int) 0x1 <<  3) /* (SPI) Clock Selection*/
#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) /* (SPI) Mode Fault Detection*/
#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) /* (SPI) Clock Selection*/
#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select*/
#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects*/
/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) /* (SPI) Receive Data*/
#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status*/
/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) /* (SPI) Transmit Data*/
#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status*/
/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) /* (SPI) Receive Data Register Full*/
#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) /* (SPI) Transmit Data Register Empty*/
#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) /* (SPI) Mode Fault Error*/
#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) /* (SPI) Overrun Error Status*/
#define AT91C_SPI_SPENDRX     ((unsigned int) 0x1 <<  4) /* (SPI) End of Receiver Transfer*/
#define AT91C_SPI_SPENDTX     ((unsigned int) 0x1 <<  5) /* (SPI) End of Receiver Transfer*/
#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) /* (SPI) RXBUFF Interrupt*/
#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) /* (SPI) TXBUFE Interrupt*/
#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) /* (SPI) Enable Status*/
/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) /* (SPI) Clock Polarity*/
#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) /* (SPI) Clock Phase*/
#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) /* (SPI) Bits Per Transfer*/
#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) /* (SPI) 8 Bits Per transfer*/
#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) /* (SPI) 9 Bits Per transfer*/
#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) /* (SPI) 10 Bits Per transfer*/
#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) /* (SPI) 11 Bits Per transfer*/
#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) /* (SPI) 12 Bits Per transfer*/
#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) /* (SPI) 13 Bits Per transfer*/
#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) /* (SPI) 14 Bits Per transfer*/
#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) /* (SPI) 15 Bits Per transfer*/
#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) /* (SPI) 16 Bits Per transfer*/
#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) /* (SPI) Serial Clock Baud Rate*/
#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate*/
#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers*/

/* ******************************************************************************/
/*              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface*/
/* ******************************************************************************/
typedef struct _AT91S_SSC {
	AT91_REG	 SSC_CR; 	/* Control Register*/
	AT91_REG	 SSC_CMR; 	/* Clock Mode Register*/
	AT91_REG	 Reserved0[2]; 	/* */
	AT91_REG	 SSC_RCMR; 	/* Receive Clock ModeRegister*/
	AT91_REG	 SSC_RFMR; 	/* Receive Frame Mode Register*/
	AT91_REG	 SSC_TCMR; 	/* Transmit Clock Mode Register*/
	AT91_REG	 SSC_TFMR; 	/* Transmit Frame Mode Register*/
	AT91_REG	 SSC_RHR; 	/* Receive Holding Register*/
	AT91_REG	 SSC_THR; 	/* Transmit Holding Register*/
	AT91_REG	 Reserved1[2]; 	/* */
	AT91_REG	 SSC_RSHR; 	/* Receive Sync Holding Register*/
	AT91_REG	 SSC_TSHR; 	/* Transmit Sync Holding Register*/
	AT91_REG	 SSC_RC0R; 	/* Receive Compare 0 Register*/
	AT91_REG	 SSC_RC1R; 	/* Receive Compare 1 Register*/
	AT91_REG	 SSC_SR; 	/* Status Register*/
	AT91_REG	 SSC_IER; 	/* Interrupt Enable Register*/
	AT91_REG	 SSC_IDR; 	/* Interrupt Disable Register*/
	AT91_REG	 SSC_IMR; 	/* Interrupt Mask Register*/
	AT91_REG	 Reserved2[44]; 	/* */
	AT91_REG	 SSC_RPR; 	/* Receive Pointer Register*/
	AT91_REG	 SSC_RCR; 	/* Receive Counter Register*/
	AT91_REG	 SSC_TPR; 	/* Transmit Pointer Register*/
	AT91_REG	 SSC_TCR; 	/* Transmit Counter Register*/
	AT91_REG	 SSC_RNPR; 	/* Receive Next Pointer Register*/
	AT91_REG	 SSC_RNCR; 	/* Receive Next Counter Register*/
	AT91_REG	 SSC_TNPR; 	/* Transmit Next Pointer Register*/
	AT91_REG	 SSC_TNCR; 	/* Transmit Next Counter Register*/
	AT91_REG	 SSC_PTCR; 	/* PDC Transfer Control Register*/
	AT91_REG	 SSC_PTSR; 	/* PDC Transfer Status Register*/
} AT91S_SSC, *AT91PS_SSC;

/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) /* (SSC) Receive Enable*/
#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) /* (SSC) Receive Disable*/
#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) /* (SSC) Transmit Enable*/
#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) /* (SSC) Transmit Disable*/
#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) /* (SSC) Software Reset*/
/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) /* (SSC) Receive/Transmit Clock Selection*/
#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) /* (SSC) Divided Clock*/
#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) /* (SSC) TK Clock signal*/
#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) /* (SSC) RK pin*/
#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) /* (SSC) Receive/Transmit Clock Output Mode Selection*/
#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only*/
#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output*/
#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output*/
#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) /* (SSC) Receive/Transmit Clock Inversion*/
#define AT91C_SSC_CKG         ((unsigned int) 0x3 <<  6) /* (SSC) Receive/Transmit Clock Gating Selection*/
#define 	AT91C_SSC_CKG_NONE                 ((unsigned int) 0x0 <<  6) /* (SSC) Receive/Transmit Clock Gating: None, continuous clock*/
#define 	AT91C_SSC_CKG_LOW                  ((unsigned int) 0x1 <<  6) /* (SSC) Receive/Transmit Clock enabled only if RF Low*/
#define 	AT91C_SSC_CKG_HIGH                 ((unsigned int) 0x2 <<  6) /* (SSC) Receive/Transmit Clock enabled only if RF High*/
#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) /* (SSC) Receive/Transmit Start Selection*/
#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.*/
#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) /* (SSC) Transmit/Receive start*/
#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) /* (SSC) Detection of a low level on RF input*/
#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) /* (SSC) Detection of a high level on RF input*/
#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) /* (SSC) Detection of a falling edge on RF input*/
#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) /* (SSC) Detection of a rising edge on RF input*/
#define 	AT91C_SSC_START_LEVEL_RF