at91rm9200.h
来自「ARM板驱动程序源代码」· C头文件 代码 · 共 909 行 · 第 1/5 页
H
909 行
/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- *//* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- *//* ******************************************************************************//* SOFTWARE API DEFINITION FOR Clock Generator Controler*//* ******************************************************************************/typedef struct _AT91S_CKGR { AT91_REG CKGR_MOR; /* Main Oscillator Register*/ AT91_REG CKGR_MCFR; /* Main Clock Frequency Register*/ AT91_REG CKGR_PLLAR; /* PLL A Register*/ AT91_REG CKGR_PLLBR; /* PLL B Register*/} AT91S_CKGR, *AT91PS_CKGR;/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable*/#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test*/#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time*//* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency*/#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready*//* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected*/#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0*/#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed*/#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter*/#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range*/#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet*/#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet*/#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet*/#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet*/#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier*/#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source*//* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected*/#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0*/#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed*/#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter*/#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range*/#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet*/#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet*/#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet*/#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet*/#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier*/#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports*/#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use*//* ******************************************************************************//* SOFTWARE API DEFINITION FOR Parallel Input Output Controler*//* ******************************************************************************/typedef struct _AT91S_PIO { AT91_REG PIO_PER; /* PIO Enable Register*/ AT91_REG PIO_PDR; /* PIO Disable Register*/ AT91_REG PIO_PSR; /* PIO Status Register*/ AT91_REG Reserved0[1]; /* */ AT91_REG PIO_OER; /* Output Enable Register*/ AT91_REG PIO_ODR; /* Output Disable Registerr*/ AT91_REG PIO_OSR; /* Output Status Register*/ AT91_REG Reserved1[1]; /* */ AT91_REG PIO_IFER; /* Input Filter Enable Register*/ AT91_REG PIO_IFDR; /* Input Filter Disable Register*/ AT91_REG PIO_IFSR; /* Input Filter Status Register*/ AT91_REG Reserved2[1]; /* */ AT91_REG PIO_SODR; /* Set Output Data Register*/ AT91_REG PIO_CODR; /* Clear Output Data Register*/ AT91_REG PIO_ODSR; /* Output Data Status Register*/ AT91_REG PIO_PDSR; /* Pin Data Status Register*/ AT91_REG PIO_IER; /* Interrupt Enable Register*/ AT91_REG PIO_IDR; /* Interrupt Disable Register*/ AT91_REG PIO_IMR; /* Interrupt Mask Register*/ AT91_REG PIO_ISR; /* Interrupt Status Register*/ AT91_REG PIO_MDER; /* Multi-driver Enable Register*/ AT91_REG PIO_MDDR; /* Multi-driver Disable Register*/ AT91_REG PIO_MDSR; /* Multi-driver Status Register*/ AT91_REG Reserved3[1]; /* */ AT91_REG PIO_PPUDR; /* Pull-up Disable Register*/ AT91_REG PIO_PPUER; /* Pull-up Enable Register*/ AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register*/ AT91_REG Reserved4[1]; /* */ AT91_REG PIO_ASR; /* Select A Register*/ AT91_REG PIO_BSR; /* Select B Register*/ AT91_REG PIO_ABSR; /* AB Select Status Register*/ AT91_REG Reserved5[9]; /* */ AT91_REG PIO_OWER; /* Output Write Enable Register*/ AT91_REG PIO_OWDR; /* Output Write Disable Register*/ AT91_REG PIO_OWSR; /* Output Write Status Register*/} AT91S_PIO, *AT91PS_PIO;/* ******************************************************************************//* SOFTWARE API DEFINITION FOR Debug Unit*//* ******************************************************************************/typedef struct _AT91S_DBGU { AT91_REG DBGU_CR; /* Control Register*/ AT91_REG DBGU_MR; /* Mode Register*/ AT91_REG DBGU_IER; /* Interrupt Enable Register*/ AT91_REG DBGU_IDR; /* Interrupt Disable Register*/ AT91_REG DBGU_IMR; /* Interrupt Mask Register*/ AT91_REG DBGU_CSR; /* Channel Status Register*/ AT91_REG DBGU_RHR; /* Receiver Holding Register*/ AT91_REG DBGU_THR; /* Transmitter Holding Register*/ AT91_REG DBGU_BRGR; /* Baud Rate Generator Register*/ AT91_REG Reserved0[7]; /* */ AT91_REG DBGU_C1R; /* Chip ID1 Register*/ AT91_REG DBGU_C2R; /* Chip ID2 Register*/ AT91_REG DBGU_FNTR; /* Force NTRST Register*/ AT91_REG Reserved1[45]; /* */ AT91_REG DBGU_RPR; /* Receive Pointer Register*/ AT91_REG DBGU_RCR; /* Receive Counter Register*/ AT91_REG DBGU_TPR; /* Transmit Pointer Register*/ AT91_REG DBGU_TCR; /* Transmit Counter Register*/ AT91_REG DBGU_RNPR; /* Receive Next Pointer Register*/ AT91_REG DBGU_RNCR; /* Receive Next Counter Register*/ AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register*/ AT91_REG DBGU_TNCR; /* Transmit Next Counter Register*/ AT91_REG DBGU_PTCR; /* PDC Transfer Control Register*/ AT91_REG DBGU_PTSR; /* PDC Transfer Status Register*/} AT91S_DBGU, *AT91PS_DBGU;/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver*/#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter*/#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable*/#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable*/#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable*/#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable*//* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */#define AT91C_US_PAR ((unsigned int) 0x7 << 9) /* (DBGU) Parity type*/#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) /* (DBGU) Even Parity*/#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) /* (DBGU) Odd Parity*/#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) /* (DBGU) Parity forced to 0 (Space)*/#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) /* (DBGU) Parity forced to 1 (Mark)*/#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity*/#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) /* (DBGU) Multi-drop mode*/#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) /* (DBGU) Channel Mode*/#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.*/#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.*/#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.*/#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.*//* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt*/#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt*/#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt*/#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt*/#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt*/#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt*/#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt*/#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt*/#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt*/#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt*/#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt*/#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt*//* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- *//* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- *//* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- *//* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) /* (DBGU) Force NTRST in JTAG*//* ******************************************************************************//* SOFTWARE API DEFINITION FOR Peripheral Data Controller*//* ******************************************************************************/typedef struct _AT91S_PDC { AT91_REG PDC_RPR; /* Receive Pointer Register*/ AT91_REG PDC_RCR; /* Receive Counter Register*/ AT91_REG PDC_TPR; /* Transmit Pointer Register*/ AT91_REG PDC_TCR; /* Transmit Counter Register*/ AT91_REG PDC_RNPR; /* Receive Next Pointer Register*/ AT91_REG PDC_RNCR; /* Receive Next Counter Register*/ AT91_REG PDC_TNPR; /* Transmit Next Pointer Register*/ AT91_REG PDC_TNCR; /* Transmit Next Counter Register*/ AT91_REG PDC_PTCR; /* PDC Transfer Control Register*/ AT91_REG PDC_PTSR; /* PDC Transfer Status Register*/} AT91S_PDC, *AT91PS_PDC;/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable*/#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) /* (PDC) Receiver Transfer Disable*/#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) /* (PDC) Transmitter Transfer Enable*/#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) /* (PDC) Transmitter Transfer Disable*//* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- *//* ******************************************************************************//* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller*/⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?