at91rm9200.h

ARM板驱动程序源代码

#define 	AT91C_MC_SIZE_16MB                 ((unsigned int) 0xE <<  4) /* (MC) Area size 16MByte*/
#define 	AT91C_MC_SIZE_64MB                 ((unsigned int) 0xF <<  4) /* (MC) Area size 64MByte*/
#define AT91C_MC_BA           ((unsigned int) 0x3FFFF << 10) /* (MC) Internal Area Base Address*/
/* -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- */
/* -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- */
#define AT91C_MC_PUEB         ((unsigned int) 0x1 <<  0) /* (MC) Protection Unit enable Bit*/

/* ******************************************************************************/
/*              SOFTWARE API DEFINITION  FOR Real-time Clock Alarm and Parallel Load Interface*/
/* ******************************************************************************/
typedef struct _AT91S_RTC {
	AT91_REG	 RTC_CR; 	/* Control Register*/
	AT91_REG	 RTC_MR; 	/* Mode Register*/
	AT91_REG	 RTC_TIMR; 	/* Time Register*/
	AT91_REG	 RTC_CALR; 	/* Calendar Register*/
	AT91_REG	 RTC_TIMALR; 	/* Time Alarm Register*/
	AT91_REG	 RTC_CALALR; 	/* Calendar Alarm Register*/
	AT91_REG	 RTC_SR; 	/* Status Register*/
	AT91_REG	 RTC_SCCR; 	/* Status Clear Command Register*/
	AT91_REG	 RTC_IER; 	/* Interrupt Enable Register*/
	AT91_REG	 RTC_IDR; 	/* Interrupt Disable Register*/
	AT91_REG	 RTC_IMR; 	/* Interrupt Mask Register*/
	AT91_REG	 RTC_VER; 	/* Valid Entry Register*/
} AT91S_RTC, *AT91PS_RTC;

/* -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- */
#define AT91C_RTC_UPDTIM      ((unsigned int) 0x1 <<  0) /* (RTC) Update Request Time Register*/
#define AT91C_RTC_UPDCAL      ((unsigned int) 0x1 <<  1) /* (RTC) Update Request Calendar Register*/
#define AT91C_RTC_TIMEVSEL    ((unsigned int) 0x3 <<  8) /* (RTC) Time Event Selection*/
#define 	AT91C_RTC_TIMEVSEL_MINUTE               ((unsigned int) 0x0 <<  8) /* (RTC) Minute change.*/
#define 	AT91C_RTC_TIMEVSEL_HOUR                 ((unsigned int) 0x1 <<  8) /* (RTC) Hour change.*/
#define 	AT91C_RTC_TIMEVSEL_DAY24                ((unsigned int) 0x2 <<  8) /* (RTC) Every day at midnight.*/
#define 	AT91C_RTC_TIMEVSEL_DAY12                ((unsigned int) 0x3 <<  8) /* (RTC) Every day at noon.*/
#define AT91C_RTC_CALEVSEL    ((unsigned int) 0x3 << 16) /* (RTC) Calendar Event Selection*/
#define 	AT91C_RTC_CALEVSEL_WEEK                 ((unsigned int) 0x0 << 16) /* (RTC) Week change (every Monday at time 00:00:00).*/
#define 	AT91C_RTC_CALEVSEL_MONTH                ((unsigned int) 0x1 << 16) /* (RTC) Month change (every 01 of each month at time 00:00:00).*/
#define 	AT91C_RTC_CALEVSEL_YEAR                 ((unsigned int) 0x2 << 16) /* (RTC) Year change (every January 1 at time 00:00:00).*/
/* -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- */
#define AT91C_RTC_HRMOD       ((unsigned int) 0x1 <<  0) /* (RTC) 12-24 hour Mode*/
/* -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- */
#define AT91C_RTC_SEC         ((unsigned int) 0x7F <<  0) /* (RTC) Current Second*/
#define AT91C_RTC_MIN         ((unsigned int) 0x7F <<  8) /* (RTC) Current Minute*/
#define AT91C_RTC_HOUR        ((unsigned int) 0x1F << 16) /* (RTC) Current Hour*/
#define AT91C_RTC_AMPM        ((unsigned int) 0x1 << 22) /* (RTC) Ante Meridiem, Post Meridiem Indicator*/
/* -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- */
#define AT91C_RTC_CENT        ((unsigned int) 0x3F <<  0) /* (RTC) Current Century*/
#define AT91C_RTC_YEAR        ((unsigned int) 0xFF <<  8) /* (RTC) Current Year*/
#define AT91C_RTC_MONTH       ((unsigned int) 0x1F << 16) /* (RTC) Current Month*/
#define AT91C_RTC_DAY         ((unsigned int) 0x7 << 21) /* (RTC) Current Day*/
#define AT91C_RTC_DATE        ((unsigned int) 0x3F << 24) /* (RTC) Current Date*/
/* -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- */
#define AT91C_RTC_SECEN       ((unsigned int) 0x1 <<  7) /* (RTC) Second Alarm Enable*/
#define AT91C_RTC_MINEN       ((unsigned int) 0x1 << 15) /* (RTC) Minute Alarm*/
#define AT91C_RTC_HOUREN      ((unsigned int) 0x1 << 23) /* (RTC) Current Hour*/
/* -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- */
#define AT91C_RTC_MONTHEN     ((unsigned int) 0x1 << 23) /* (RTC) Month Alarm Enable*/
#define AT91C_RTC_DATEEN      ((unsigned int) 0x1 << 31) /* (RTC) Date Alarm Enable*/
/* -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- */
#define AT91C_RTC_ACKUPD      ((unsigned int) 0x1 <<  0) /* (RTC) Acknowledge for Update*/
#define AT91C_RTC_ALARM       ((unsigned int) 0x1 <<  1) /* (RTC) Alarm Flag*/
#define AT91C_RTC_SECEV       ((unsigned int) 0x1 <<  2) /* (RTC) Second Event*/
#define AT91C_RTC_TIMEV       ((unsigned int) 0x1 <<  3) /* (RTC) Time Event*/
#define AT91C_RTC_CALEV       ((unsigned int) 0x1 <<  4) /* (RTC) Calendar event*/
/* -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- */
/* -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- */
/* -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- */
/* -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- */
/* -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- */
#define AT91C_RTC_NVTIM       ((unsigned int) 0x1 <<  0) /* (RTC) Non valid Time*/
#define AT91C_RTC_NVCAL       ((unsigned int) 0x1 <<  1) /* (RTC) Non valid Calendar*/
#define AT91C_RTC_NVTIMALR    ((unsigned int) 0x1 <<  2) /* (RTC) Non valid time Alarm*/
#define AT91C_RTC_NVCALALR    ((unsigned int) 0x1 <<  3) /* (RTC) Nonvalid Calendar Alarm*/

/* ******************************************************************************/
/*              SOFTWARE API DEFINITION  FOR System Timer Interface*/
/* ******************************************************************************/
typedef struct _AT91S_ST {
	AT91_REG	 ST_CR; 	/* Control Register*/
	AT91_REG	 ST_PIMR; 	/* Period Interval Mode Register*/
	AT91_REG	 ST_WDMR; 	/* Watchdog Mode Register*/
	AT91_REG	 ST_RTMR; 	/* Real-time Mode Register*/
	AT91_REG	 ST_SR; 	/* Status Register*/
	AT91_REG	 ST_IER; 	/* Interrupt Enable Register*/
	AT91_REG	 ST_IDR; 	/* Interrupt Disable Register*/
	AT91_REG	 ST_IMR; 	/* Interrupt Mask Register*/
	AT91_REG	 ST_RTAR; 	/* Real-time Alarm Register*/
	AT91_REG	 ST_CRTR; 	/* Current Real-time Register*/
} AT91S_ST, *AT91PS_ST;

/* -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- */
#define AT91C_ST_WDRST        ((unsigned int) 0x1 <<  0) /* (ST) Watchdog Timer Restart*/
/* -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- */
#define AT91C_ST_PIV          ((unsigned int) 0xFFFF <<  0) /* (ST) Watchdog Timer Restart*/
/* -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- */
#define AT91C_ST_WDV          ((unsigned int) 0xFFFF <<  0) /* (ST) Watchdog Timer Restart*/
#define AT91C_ST_RSTEN        ((unsigned int) 0x1 << 16) /* (ST) Reset Enable*/
#define AT91C_ST_EXTEN        ((unsigned int) 0x1 << 17) /* (ST) External Signal Assertion Enable*/
/* -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- */
#define AT91C_ST_RTPRES       ((unsigned int) 0xFFFF <<  0) /* (ST) Real-time Timer Prescaler Value*/
/* -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- */
#define AT91C_ST_PITS         ((unsigned int) 0x1 <<  0) /* (ST) Period Interval Timer Interrupt*/
#define AT91C_ST_WDOVF        ((unsigned int) 0x1 <<  1) /* (ST) Watchdog Overflow*/
#define AT91C_ST_RTTINC       ((unsigned int) 0x1 <<  2) /* (ST) Real-time Timer Increment*/
#define AT91C_ST_ALMS         ((unsigned int) 0x1 <<  3) /* (ST) Alarm Status*/
/* -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- */
/* -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- */
/* -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- */
/* -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- */
#define AT91C_ST_ALMV         ((unsigned int) 0xFFFFF <<  0) /* (ST) Alarm Value Value*/
/* -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- */
#define AT91C_ST_CRTV         ((unsigned int) 0xFFFFF <<  0) /* (ST) Current Real-time Value*/

/* ******************************************************************************/
/*              SOFTWARE API DEFINITION  FOR Power Management Controler*/
/* ******************************************************************************/
typedef struct _AT91S_PMC {
	AT91_REG	 PMC_SCER; 	/* System Clock Enable Register*/
	AT91_REG	 PMC_SCDR; 	/* System Clock Disable Register*/
	AT91_REG	 PMC_SCSR; 	/* System Clock Status Register*/
	AT91_REG	 Reserved0[1]; 	/* */
	AT91_REG	 PMC_PCER; 	/* Peripheral Clock Enable Register*/
	AT91_REG	 PMC_PCDR; 	/* Peripheral Clock Disable Register*/
	AT91_REG	 PMC_PCSR; 	/* Peripheral Clock Status Register*/
	AT91_REG	 Reserved1[5]; 	/* */
	AT91_REG	 PMC_MCKR; 	/* Master Clock Register*/
	AT91_REG	 Reserved2[3]; 	/* */
	AT91_REG	 PMC_PCKR[8]; 	/* Programmable Clock Register*/
	AT91_REG	 PMC_IER; 	/* Interrupt Enable Register*/
	AT91_REG	 PMC_IDR; 	/* Interrupt Disable Register*/
	AT91_REG	 PMC_SR; 	/* Status Register*/
	AT91_REG	 PMC_IMR; 	/* Interrupt Mask Register*/
} AT91S_PMC, *AT91PS_PMC;

/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) /* (PMC) Processor Clock*/
#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  1) /* (PMC) USB Device Port Clock*/
#define AT91C_PMC_MCKUDP      ((unsigned int) 0x1 <<  2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend*/
#define AT91C_PMC_UHP         ((unsigned int) 0x1 <<  4) /* (PMC) USB Host Port Clock*/
#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) /* (PMC) Programmable Clock Output*/
#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) /* (PMC) Programmable Clock Output*/
#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output*/
#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output*/
#define AT91C_PMC_PCK4        ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output*/
#define AT91C_PMC_PCK5        ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output*/
#define AT91C_PMC_PCK6        ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output*/
#define AT91C_PMC_PCK7        ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output*/
/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) /* (PMC) Programmable Clock Selection*/
#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) /* (PMC) Slow Clock is selected*/
#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) /* (PMC) Main Clock is selected*/
#define 	AT91C_PMC_CSS_PLLA_CLK             ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected*/
#define 	AT91C_PMC_CSS_PLLB_CLK             ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected*/
#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) /* (PMC) Programmable Clock Prescaler*/
#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) /* (PMC) Selected clock*/
#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) /* (PMC) Selected clock divided by 2*/
#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) /* (PMC) Selected clock divided by 4*/
#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) /* (PMC) Selected clock divided by 8*/
#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) /* (PMC) Selected clock divided by 16*/
#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) /* (PMC) Selected clock divided by 32*/
#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) /* (PMC) Selected clock divided by 64*/
#define AT91C_PMC_MDIV        ((unsigned int) 0x3 <<  8) /* (PMC) Master Clock Division*/
#define 	AT91C_PMC_MDIV_1                    ((unsigned int) 0x0 <<  8) /* (PMC) The master clock and the processor clock are the same*/
#define 	AT91C_PMC_MDIV_2                    ((unsigned int) 0x1 <<  8) /* (PMC) The processor clock is twice as fast as the master clock*/
#define 	AT91C_PMC_MDIV_3                    ((unsigned int) 0x2 <<  8) /* (PMC) The processor clock is three times faster than the master clock*/
#define 	AT91C_PMC_MDIV_4                    ((unsigned int) 0x3 <<  8) /* (PMC) The processor clock is four times faster than the master clock*/
/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) /* (PMC) MOSC Status/Enable/Disable/Mask*/
#define AT91C_PMC_LOCKA       ((unsigned int) 0x1 <<  1) /* (PMC) PLL A Status/Enable/Disable/Mask*/
#define AT91C_PMC_LOCKB       ((unsigned int) 0x1 <<  2) /* (PMC) PLL B Status/Enable/Disable/Mask*/
#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK4RDY     ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK5RDY     ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK6RDY     ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK7RDY     ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask*/
/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */