fp_forfpga.txt

用于FPGA的Ｎ＋０.５分频代码

--########################顶层实体##########################################                                                 
-
--************************记录*********************************************
--  LOGIC CORE:          RTL module
--  MODULE NAME:         divfre

--  COMPANY:             Altera  
--  AUTHOR:              YJP       

--  TIME:                7.15.2008
--  Copyright:            

-- 

-- 功能简述:    

--
 n+0.5分频   
-- 例如输入n=7，则实现6.5分频
--
--
--
--
--
--********************定义端口***********************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
--
entity divfre is
port(
     clk_s   	 : in std_logic;
     rst    	 : in std_logic;
     N           : in std_logic_vector(15 downto 0);
     clk_div	 : buffer std_logic;
     sel         : in std_logic
);
end divfre;
--
--
architecture rtl of divfre is
--
--
signal cnt1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal re2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal clk2,clk: std_logic;
--
begin
--
--
clk <= clk_s xor clk2;
process(clk,rst,sel)
   begin
    if rst = '0' or sel = '0'then 
       cnt1 <=x"0001";
     elsif clk'event and clk='1' then
           if cnt1 = N then
                cnt1 <= x"0001";
                clk_div <= '1';
           else cnt1 <= cnt1+1;
                clk_div <= '0';
           end if;
     end if;
end process;
--
--
process(clk_div,rst,sel)
     begin
        if rst = '0' or sel = '0' then
             clk2 <= '0' ;
        elsif clk_div'event and clk_div='1' then
             clk2 <= not clk2;
        end if;
end process;
--
--
end rtl;