count__10.tan.qmsg

这是VERILOG语言编写的程序,可在FPGA板上运行.有很大的作用.谢谢.

{ "Info" "ITDB_TH_RESULT" "qout\[0\]~reg0 data\[0\] clk -2.350 ns register " "Info: th for register \"qout\[0\]~reg0\" (data pin = \"data\[0\]\", clock pin = \"clk\") is -2.350 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.872 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.502 ns) + CELL(0.542 ns) 2.872 ns qout\[0\]~reg0 2 REG LC_X41_Y30_N4 6 " "Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout\[0\]~reg0'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.044 ns" { clk qout[0]~reg0 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.70 % ) " "Info: Total cell delay = 1.370 ns ( 47.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.502 ns ( 52.30 % ) " "Info: Total interconnect delay = 1.502 ns ( 52.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.872 ns" { clk qout[0]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 qout[0]~reg0 } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.322 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.322 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns data\[0\] 1 PIN PIN_H8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_H8; Fanout = 1; PIN Node = 'data\[0\]'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { data[0] } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.696 ns) + CELL(0.539 ns) 5.322 ns qout\[0\]~reg0 2 REG LC_X41_Y30_N4 6 " "Info: 2: + IC(3.696 ns) + CELL(0.539 ns) = 5.322 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout\[0\]~reg0'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "4.235 ns" { data[0] qout[0]~reg0 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.626 ns ( 30.55 % ) " "Info: Total cell delay = 1.626 ns ( 30.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.696 ns ( 69.45 % ) " "Info: Total interconnect delay = 3.696 ns ( 69.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "5.322 ns" { data[0] qout[0]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "5.322 ns" { data[0] data[0]~out0 qout[0]~reg0 } { 0.000ns 0.000ns 3.696ns } { 0.000ns 1.087ns 0.539ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.872 ns" { clk qout[0]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 qout[0]~reg0 } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "5.322 ns" { data[0] qout[0]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "5.322 ns" { data[0] data[0]~out0 qout[0]~reg0 } { 0.000ns 0.000ns 3.696ns } { 0.000ns 1.087ns 0.539ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 29 12:18:48 2009 " "Info: Processing ended: Sun Mar 29 12:18:48 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}