base_addr_chk.v

基于FPGA的PCI接口设计的源代码以及其仿真测试文件

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// Copyright (c) 2001 by Lattice Semiconductor Corporation
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//   This VHDL or Verilog source code is intended as a design reference
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// Revision History :
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//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   v1.0 :| D.S.              :| 12/14/98  :| Initial Creation
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//
//	Module  base_addr_chk
//
/*    This block is called the base_addr_chk block, and it's purpose is to
      implement the write only portion of the base address registers BA0 and
      BA1.   BA0 and BA1 registers are system programmable, and used to
      decode the start of the base address regions of the backend device.
      When a write is performed  on BA0 or BA1 the registers in this
      block latch the data.
      When they are read, the system is determining the amount of address
      space required by the back end device. The BA0 and BA1 Read-Only
      registers contain the size of the address space, and are set BY THE
      DESIGNER in the config_mux block. The outputs of that block are
      inputs to this block. 
      They are used to determine if the address being requested is a
      hit on the target.  The hit_ba0_l and hit_ba1_l are inputs to
      the state machine to tell it to assert dev_sel_l. 
*/
//
//
module base_addr_chk (hit_ba0_l, hit_ba1_l, ba0_size, 
                      ba1_size, pci_ad, pci_addr, ba0_en, 
		      ba1_en, pci_clk, pci_rst_l,
		      //JO ADD
		      ba0_rw_reg, ba1_rw_reg, pci_cbe_l
		      //END JO ADD
		      );
		      
  output hit_ba0_l; // active low output telling the statemachine the
		    // address is a hit in base address 0
  output hit_ba1_l; // active low output telling the statemachine the
		    // address is a hit in base address 1
  input [31:4] ba0_size; // The user defined size bits from the config_mux block
  input [31:4] ba1_size; // The user defined size bits from the config_mux block
  input [31:4] pci_ad; // The raw pci_ad data 
  input [31:4] pci_addr; // The pci address registered
  input ba0_en; // base address 0 clock enable
  input ba1_en; // base address 1 clock enable
  input pci_clk; // The pci_clk
  input pci_rst_l; // The asynchronous reset active low

  reg [31:4] ba0, ba1; // the write only BA0 and BA1 registers

  //JO ADD
  input [3:0] pci_cbe_l;
  output [31:0] ba0_rw_reg; 
  output [31:0] ba1_rw_reg;
  assign ba0_rw_reg = {ba0, 4'b0000};
  assign ba1_rw_reg = {ba1, 4'b0000};
  //END JO ADD
 
 wire hit_ba0_l;
 wire hit_ba1_l;
 

 
 
  // The following block contains the write only BA0 and BA1 registers
  // The system software will map the assigned base address into these
  // registers.
  
  always @ (posedge pci_clk or negedge pci_rst_l)
    begin 
      if (pci_rst_l == 1'b0) begin 
	  ba0 <= 28'h0;
	  ba1 <= 28'h0;
	end
      else if (ba0_en == 1'b1) begin 
          //JO REM
          //ba0 <= pci_ad[31:4]; // write the base address during a config cycle
          //END JO REM
          //JO ADD
          if (!pci_cbe_l[3])
             ba0[31:24] <= pci_ad[31:24]; // write the base address during a config cycle

	  if (!pci_cbe_l[2])
             ba0[23:16] <= pci_ad[23:16]; // write the base address during a config cycle

	  if (!pci_cbe_l[1])
             ba0[15:8] <= pci_ad[15:8]; // write the base address during a config cycle

	  if (!pci_cbe_l[0])
             ba0[7:4] <= pci_ad[7:4]; // write the base address during a config cycle
      //END JO ADD
      end
      else if (ba1_en == 1'b1) begin 
	  //JO REM
	  //ba1 <= pci_ad[31:4]; // write the base address during a config cycle
	  //END JO REM
	  //JO ADD
	  if (!pci_cbe_l[3])
             ba1[31:24] <= pci_ad[31:24]; // write the base address during a config cycle

	  if (!pci_cbe_l[2])
             ba1[23:16] <= pci_ad[23:16]; // write the base address during a config cycle

	  if (!pci_cbe_l[1])
             ba1[15:8] <= pci_ad[15:8]; // write the base address during a config cycle

	  if (!pci_cbe_l[0])
             ba1[7:4] <= pci_ad[7:4]; // write the base address during a config cycle
    //END JO ADD
      end
  //JO REM
  //    else begin 
	//ba0 <= ba0;
	//ba1 <= ba1;
      //end  
  	//END JO REM
    end
 
 // The following block is the decode used to determine if 
 // the address in the PCI address reg is a located in Base Address Region 0 or 1
 
 // What happens here...the size is passed from the config_mux block
 // The 1's are bit's to be decoded and the 0's are don't cares.
 // Example:
 // FFF0_0000 = 1M addressable space so only decode the top 12 bits.
 // a bit wise "and" is done to 0 out lower order bits.
 
 assign hit_ba0_l = (pci_addr & ba0_size) == ba0 ? 0 : 1;
 assign hit_ba1_l = (pci_addr & ba1_size) == ba1 ? 0 : 1;
  
  
endmodule  //of base_addr_chk