📄 state_machine.v
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base_region0_l <= #1 1; // disable
base_region1_l <= #1 0; // enable
dts_oe <= #13 1; // takes 1 tic get ready to drive
devsel_l <= #1 1; // disabled at first
trdy_l <= #1 1; // disabled at first
stop_l <= #1 1; // disabled at first
if (read_flag) begin
bk_oe <= #13 0; // disable OE
r_w_l <= #1 1;
end
else begin
bk_oe <= #13 1; // enable OE
r_w_l <= #1 0;
end
end
else begin // No hit
cstate <= #1 idle;
bk_oe <= #13 0; // disable OE
count_rst_l <= #1 1; // disable
count_en_l <= #1 1; // disable
r_w_l <= #1 1; // default to read
base_region0_l <= #1 1; // disable
base_region1_l <= #1 1; // disable
dts_oe <= #13 0; // disable
devsel_l <= #1 1; // disabled
trdy_l <= #1 1; // disabled
stop_l <= #1 1; // disabled
end
end
/* In the rw_wait2 state we can now activate
devsel_l trdy_l or stop. We had to wait for
the OE to stabalize before this.
*/
rw_wait2: // don't monitor abort here
begin
if (read_flag) begin
pci_ad_oe <= #13 1; // enable
par_oe <= #13 1; // enable
end
else begin
pci_ad_oe <= #13 0; // disable
end
if (!retry_l) begin
// retry timeout
cstate <= #1 retry;
devsel_l <= #1 0;
trdy_l <= #1 1;
stop_l <= #1 0;
end
else if (retry_l && !ready_l && !pci_frame_l && data_stop_l) begin
// normal burst write or read with no timeout or stop
devsel_l <= #1 0;
stop_l <= #1 1;
if (read_flag) begin // read
cstate <= read_wait;
trdy_l <= #1 1;
end
else begin // write
cstate <= rw;
trdy_l <= #1 0;
end
end
else if (retry_l && !ready_l && pci_frame_l) begin
// single read or write with no timeout & stop is don't care
devsel_l <= #1 0;
stop_l <= #1 1;
if (read_flag) begin // read
cstate <= read_wait;
trdy_l <= #1 1;
end
else begin // write
cstate <= last_rw;
trdy_l <= #1 0;
end
end
else if (retry_l && !ready_l && !data_stop_l) begin
// single read or write & backend only wants one cycle
if (read_flag ) begin
cstate <= read_wait;
devsel_l <= #1 0;
trdy_l <= #1 1;
stop_l <= #1 1;
end
else begin
cstate <= last_rw; // disconnect B
devsel_l <= #1 0;
trdy_l <= #1 0;
stop_l <= #1 0;
end
end
else if (retry_l && ready_l) begin
// enable retry counter
cstate <= #1 rw_wait2;
count_en_l <= #1 0;
devsel_l <= #1 0;
trdy_l <= #1 1;
stop_l <= #1 1;
end
else if (!bkend_abort_l) begin
cstate <= #1 abort;
devsel_l <= #1 1;
trdy_l <= #1 1;
stop_l <= #1 0;
abort_sig <= #1 1;
end
else begin
cstate <= rw_wait2;
end
end
read_wait:
//This state is used to READ the first piece of data
begin // from the backend device BEFORE asserting trdy_l
if ( !bkend_abort_l) begin
cstate <= #1 abort;
devsel_l <= #1 1;
trdy_l <= #1 1;
stop_l <= #1 0;
bk_oe <= #13 0;
base_region0_l <= #1 1; // disable
base_region1_l <= #1 1; // disable
abort_sig <= #1 1;
end
else if (!pci_frame_l && bkend_abort_l && data_stop_l) begin
cstate <= #1 rw; // burst
devsel_l <= #1 0;
trdy_l <= #1 0;
stop_l <= #1 1;
end
else if (pci_frame_l && bkend_abort_l && data_stop_l) begin
cstate <= #1 last_rw; // single cycle
devsel_l <= #1 0;
trdy_l <= #1 0;
stop_l <= #1 1;
end
else if (!data_stop_l) begin
cstate <= last_rw;// disconnect A
devsel_l <= #1 0;
trdy_l <= #1 0;
stop_l <= #1 0;
bk_oe <= #13 0;
end
else begin
cstate <= idle;
end
end
rw:
begin
if ( !bkend_abort_l) begin
cstate <= #1 abort;
devsel_l <= #1 1;
trdy_l <= #1 1;
stop_l <= #1 0;
bk_oe <= #13 0; // disable OE
base_region0_l <= #1 1; // disable
base_region1_l <= #1 1; // disable
abort_sig <= #1 1;
end
else if (!pci_frame_l && bkend_abort_l && data_stop_l) begin
cstate <= #1 rw;
devsel_l <= #1 0;
trdy_l <= #1 0;
stop_l <= #1 1;
end
else if (pci_frame_l && bkend_abort_l && data_stop_l) begin
cstate <= #1 backoff;
devsel_l <= #1 1;
trdy_l <= #1 1;
stop_l <= #1 1;
pci_ad_oe <= #13 0;
bk_oe <= #13 0; // disable OE
base_region0_l <= #1 1; // disable
base_region1_l <= #1 1; // disable
end
else if (pci_frame_l && !data_stop_l) begin
cstate <= backoff;
devsel_l <= #1 1;
trdy_l <= #1 1;
stop_l <= #1 1;
bk_oe <= #13 0; // disable OE
base_region0_l <= #1 1; // disable
base_region1_l <= #1 1; // disable
end
else if (!data_stop_l) begin
cstate <= last_rw; // disconnect A
devsel_l <= #1 0;
trdy_l <= #1 0;
stop_l <= #1 0;
end
else begin
cstate <= idle;
end
end
last_rw:
begin
if (pci_frame_l) begin
// pci_frame_l end gracefully
cstate <= backoff;
devsel_l <= #1 1;
trdy_l <= #1 1;
stop_l <= #1 1;
bk_oe <= #13 0; // disable OE
pci_ad_oe <= #13 0;
base_region0_l <= #1 1; // disable
base_region1_l <= #1 1; // disable
end
else if (!pci_frame_l) begin
// !data_stop_l wait for pci_frame_l
cstate <= last_rw; // continue disconnect A
devsel_l <= #1 0;
trdy_l <= #1 1;
stop_l <= #1 0;
end
else begin
cstate <= idle;
end
end
retry:
begin
if (!pci_frame_l) begin
cstate <= retry;
dts_oe <= #13 1;
devsel_l <= #1 0;
trdy_l <= #1 1;
stop_l <= #1 0;
bk_oe <= #13 0; // disable OE
base_region0_l <= #1 1; // disable
base_region1_l <= #1 1; // disable
end
else if (pci_frame_l) begin
cstate <= backoff;
devsel_l <= #1 1;
trdy_l <= #1 1;
stop_l <= #1 1;
bk_oe <= #13 0; // disable OE
pci_ad_oe <= #13 0;
base_region0_l <= #1 1; // disable
base_region1_l <= #1 1; // disable
end
end
abort:
begin
if (!pci_frame_l) begin
cstate <= abort;
devsel_l <= #1 1;
trdy_l <= #1 1;
stop_l <= #1 0;
abort_sig <= #1 0;// disable
end
else if (pci_frame_l) begin
cstate <= backoff;
devsel_l <= #1 1;
trdy_l <= #1 1;
stop_l <= #1 1;
bk_oe <= #13 0;
pci_ad_oe <= #13 0;
abort_sig <= #1 0; // disable
end
end
backoff:
begin
cstate <= idle;
pci_ad_oe <= #13 0; // disable
dts_oe <= #13 0; //disable
par_oe <= #13 0; // disable
bk_oe <=#13 0; // disable
end
default:
begin
cstate <= #1 idle;
devsel_l <= #1 1;
trdy_l <= #1 1;
stop_l <= #1 1;
pci_ad_oe <= #13 0;
dts_oe <= #13 0;
par_oe <= #13 0;
bk_oe <= #13 0;
abort_sig <= #1 0;
end
endcase
end
end
/************************************************/
/* The following block contains the byte enable */
/* for the back end */
/************************************************/
always @ (cstate)
begin
if (cstate == idle || cstate == backoff) begin
be_oe <= #1 0;
end
else begin
be_oe <= #1 1;
end
end
/*********************************************/
/* The following block contains clock */
/* enables for specific system registers */
/*********************************************/
always @ (pci_frame_l or cstate)
begin
if (cstate == idle && !pci_frame_l) begin
pci_ad_en <= #1 1;
end
else begin
pci_ad_en <= #1 0;
end
end
/*************************************************************************/
/* The back end device is allowed initial cycle latencey,
but once the cycle is started it must continue, or stop the transaction.
Once the backend is ready it will signal !ready_l.
The PCI state machine will assert trdy_l.
The following two signals data_write_l and data_read_l are the only
outputs of the block that are not registered.
*/
/*************************************************************************/
// The write strobe for the backend device
assign #1 data_write_l = (!trdy_l && !pci_irdy_l && !read_flag && !ready_l) ? 0 : 1;
// The read strobe for the backend device
assign #1 data_read_l = ( (single_read_flag && (cstate == rw_wait2) && !ready_l ) || (!single_read_flag && read_flag && !pci_frame_l && !pci_irdy_l && !ready_l && (cstate == rw_wait2 || cstate == rw || cstate == last_rw || cstate == abort)) ) ? 0 : 1;
endmodule //of state_machine
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