test_bench.v

PCI IP核功能实现

                    { `WB_CONFIGURATION_BASE, `W_TA2_ADDR },				
                    { `WB_CONFIGURATION_BASE, `W_TA3_ADDR },				
                    { `WB_CONFIGURATION_BASE, `W_TA4_ADDR },				
                    { `WB_CONFIGURATION_BASE, `W_TA5_ADDR }:if (read_data !== 32'hFFFF_F000)
                                                                display_warning(current_address, 32'hFFFF_F000, read_data) ;    

                    { `WB_CONFIGURATION_BASE, `W_ERR_CS_ADDR }:if (read_data !== 32'h0000_0001)
                                                                    display_warning(current_address, 32'h0000_0001, read_data) ;     
                                                                        
                    { `WB_CONFIGURATION_BASE, `W_ERR_ADDR_ADDR }:   if (read_data !== 32'h0000_0000)
                                                                        display_warning(current_address, 32'h0000_0000, read_data) ;    
    
                    { `WB_CONFIGURATION_BASE, `W_ERR_DATA_ADDR }:   if (read_data !== 32'h0000_0000)
                                                                        display_warning(current_address, 32'h0000_0000, read_data) ;    

                    { `WB_CONFIGURATION_BASE, `CNF_ADDR_ADDR }: if (read_data !== 32'h00FF_FFFD)
                                                                    display_warning(current_address, 32'h00FF_FFFD, read_data) ;    

                    { `WB_CONFIGURATION_BASE, `ICR_ADDR }:  if (read_data !== 32'h8000_000F)
                                                                display_warning(current_address, 32'h8000_000F, read_data) ;    

                    { `WB_CONFIGURATION_BASE, `ISR_ADDR }:  if (read_data !== 32'h0000_0000)
                                                                display_warning(current_address, 32'h0000_0000, read_data) ;    

                    default:// access to unimplemented space  
                            if (read_data !== 32'h0000_0000)
                                display_warning(current_address, 32'h0000_0000, read_data) ;    
                endcase
            end // transfer acknowledged
            
            // increment burst address
            current_address = current_address + 4 ;
            
            i = i + 1 ;
        end //while
        
        // check if whole access was done succesfully
        if (i < 1024)
            $display("WISHBONE slave responded with error or retry too early! It didn't allow whole configuration space access!") ;
        
        @(posedge wb_clock) ;

        $display("Configuration space test done") ;

    end
endtask //conf_space_test 

task wb_error_log_test;
    reg [31:0] current_address ;
    reg [2:0] result ;
    reg [31:0] read_data ;

begin
        $display("Starting WISHBONE error reporting test!") ;
        
        // error is set on pci_clock, since PCI Master is reporting it
        @(posedge pci_clock) ;
        
        // signal an error
        wb_error_sig  <= #`FF_DELAY 1'b1 ;
        // define error source
        wb_error_es   <= #`FF_DELAY 1'b1 ;

        //provide address and data of the access when error occured
        wb_error_addr <= #`FF_DELAY 32'hFFFF_FFFF ;
        wb_error_data <= #`FF_DELAY 32'hFFFF_FFFF ;
        
        // provide byte enables and bus command of an access
        wb_error_be <= #`FF_DELAY 4'hF ;
        wb_error_bc <= #`FF_DELAY 4'hF ;

        // wait for posedge
        // here error should be written to registers
        @(posedge pci_clock) ;
    
        // dismiss error generation and change data values also
        wb_error_sig  <= #`FF_DELAY 1'b0 ;
        wb_error_es   <= #`FF_DELAY 1'b0 ;
        wb_error_addr <= #`FF_DELAY 32'h0000_0000 ;
        wb_error_data <= #`FF_DELAY 32'h0000_0000 ;
        wb_error_be <= #`FF_DELAY 4'h0 ;
        wb_error_bc <= #`FF_DELAY 4'h0 ;

        // wait for negedge - give FFs and outputs enough setup time
        @(negedge pci_clock) ;
        
        // first check corresponding outputs from configuration space
        if (~wb_error_sig_set)
            $display("WISHBONE error pending output didn't have a value of 1 when error was signalled!") ;

        // now do a read from these registers and see if right data is provided
        // read from error control and status register
        current_address = { `WB_CONFIGURATION_BASE, `W_ERR_CS_ADDR } ;
        wishbone_master.blkrd( current_address, 4'hF, 1'b0, 1'b1, 1'b0, {result, read_data} ) ;

        if (result[2]) 
        begin
            if (read_data !== 32'hFF00_0301)
                display_warning(current_address, 32'hFF00_0301, read_data) ;    
        end
        else
            $display("WISHBONE slave didn't acknowledge an access to address %h although it was expected to!", current_address) ;

        //read from error data register
        current_address = { `WB_CONFIGURATION_BASE, `W_ERR_DATA_ADDR } ;
        wishbone_master.blkrd( current_address, 4'hF, 1'b0, 1'b0, 1'b0, {result, read_data} ) ;

        if (result[2]) 
        begin
            if (read_data !== 32'hFFFF_FFFF)
                display_warning(current_address, 32'hFFFF_FFFF, read_data) ;    
        end
        else
            $display("WISHBONE slave didn't acknowledge an access to address %h although it was expected to!", current_address) ;

        // read from error address register
        current_address = { `WB_CONFIGURATION_BASE, `W_ERR_ADDR_ADDR } ;
        wishbone_master.blkrd( current_address, 4'hF, 1'b0, 1'b0, 1'b1, {result, read_data} ) ;

        if (result[2]) 
        begin
            if (read_data !== 32'hFFFF_FFFF)
                display_warning(current_address, 32'hFFFF_FFFF, read_data) ;    
        end
        else
            $display("WISHBONE slave didn't acknowledge an access to address %h although it was expected to!", current_address) ;

        // now write one to corresponding status bit and see if it turns off
        // do a write
        current_address = { `WB_CONFIGURATION_BASE, `W_ERR_CS_ADDR } ;
        wishbone_master.blkwr( current_address + 1, 32'h0000_0100, 4'b0010, 1'b0, 1'b1, 1'b0, result ) ;
        
        // check if access was acknowledged
        if (~result[2])
            $display("WISHBONE slave didn't acknowledge an access to address %h although it was expected to!", current_address) ;
        
        @(negedge wb_clock) ;

        // probe for error pending output
        if (wb_error_sig_set)
            $display("WISHBONE error pending output didn't have a value of 0 when cleared by writing 1 to it!") ;
        
        // now do a read from same register
        current_address = { `WB_CONFIGURATION_BASE, `W_ERR_CS_ADDR } ;
        wishbone_master.blkrd( current_address, 4'hF, 1'b0, 1'b0, 1'b1, {result, read_data} ) ;

        if (result[2]) 
        begin
            if (read_data !== 32'hFF00_0201)
                display_warning(current_address, 32'hFF00_0201, read_data) ;    
        end
        else
            $display("WISHBONE slave didn't acknowledge an access to address %h although it was expected to!", current_address) ;

        // do a test of retry error signalization
        @(posedge pci_clock) ;

        // signal an error
        wb_error_rty_exp <= #`FF_DELAY 1'b1 ;
        
        // wait for posedge
        // here error is written to register
        @(posedge pci_clock) ;
    
        // dismiss error generation
        wb_error_rty_exp <= #`FF_DELAY 1'b0 ;

        // wait for negedge - give FFs and outputs enough setup time
        @(negedge pci_clock) ;
        
        // first check corresponding outputs from configuration space
        if (~wb_error_rty_exp_set)
            $display("WISHBONE retry expired output didn't show a value of 1 when retry expired was signaled") ;

        // now do a read from these registers and see if right data is provided
        
        // read from error control and status register
        current_address = { `WB_CONFIGURATION_BASE, `W_ERR_CS_ADDR } ;
        wishbone_master.blkrd( current_address, 4'hF, 1'b0, 1'b1, 1'b0, {result, read_data} ) ;

        if (result[2]) 
        begin
            if (read_data !== 32'hFF00_0601)
                display_warning(current_address, 32'hFF00_0601, read_data) ;    
        end
        else
            $display("WISHBONE slave didn't acknowledge an access to address %h although it was expected to!", current_address) ;

        //read from error data register
        current_address = { `WB_CONFIGURATION_BASE, `W_ERR_DATA_ADDR } ;
        wishbone_master.blkrd( current_address, 4'hF, 1'b0, 1'b0, 1'b0, {result, read_data} ) ;

        if (result[2]) 
        begin
            if (read_data !== 32'hFFFF_FFFF)
                display_warning(current_address, 32'hFFFF_FFFF, read_data) ;    
        end
        else
            $display("WISHBONE slave didn't acknowledge an access to address %h although it was expected to!", current_address) ;

        // read from error address register
        current_address = { `WB_CONFIGURATION_BASE, `W_ERR_ADDR_ADDR } ;
        wishbone_master.blkrd( current_address, 4'hF, 1'b0, 1'b0, 1'b1, {result, read_data} ) ;

        if (result[2]) 
        begin
            if (read_data !== 32'hFFFF_FFFF)
                display_warning(current_address, 32'hFFFF_FFFF, read_data) ;    
        end
        else
            $display("WISHBONE slave didn't acknowledge an access to address %h although it was expected to!", current_address) ;

        // now write one to corresponding status bit and see if it turns off
        // do a write
        current_address = { `WB_CONFIGURATION_BASE, `W_ERR_CS_ADDR } ;
        wishbone_master.blkwr( current_address, 32'hFFFF_FFFF, 4'hF, 1'b0, 1'b1, 1'b0, result ) ;

        // check if transfer was acknowledged
        if (~result[2])
            $display("WISHBONE slave didn't acknowledge an access to address %h although it was expected to!", current_address) ;
        
        @(negedge pci_clock) ;
        // probe for error pending output
        if (wb_error_rty_exp_set)
            $display("WISHBONE retry expired error output wasn't cleared when 1 was written to its location") ;
        
        // now do a read from same register
        current_address = { `WB_CONFIGURATION_BASE, `W_ERR_CS_ADDR } ;
        wishbone_master.blkrd( current_address, 4'hF, 1'b0, 1'b1, 1'b1, {result, read_data} ) ;

        if (result[2]) 
        begin
            if (read_data !== 32'hFF00_0201)
                display_warning(current_address, 32'hFF00_0201, read_data) ;    
        end
        else
            $display("WISHBONE slave didn't acknowledge an access to address %h although it was expected to!", current_address) ;

        $display("WISHBONE error reporting test finished!") ;
end
endtask //wb_error_log_test

task pci_error_log_test;
    reg [31:0] current_address ;
    reg [2:0] result ;
    reg [31:0] read_data ;
begin
        // PCI error signaling test - WISHBONE master does it so it's sync'd to WISHBONE clock
        
        $display("Starting PCI error reporting test!") ;
        
        @(posedge wb_clock) ;
        
        // signal an error
        pci_error_sig  <= #`FF_DELAY 1'b1 ;
        
        //provide address and data of the access when error occured
        pci_error_addr <= #`FF_DELAY 32'hFFFF_FFFF ;
        pci_error_data <= #`FF_DELAY 32'hFFFF_FFFF ;
        
        // provide byte enables and bus command of an access
        pci_error_be <= #`FF_DELAY 4'hF ;
        pci_error_bc <= #`FF_DELAY 4'hF ;

        // wait for posedge
        // here error is written to registers
        @(posedge wb_clock) ;
    
        // dismiss error generation and data inputs
        pci_error_sig  <= #`FF_DELAY 1'b0 ;
        pci_error_addr <= #`FF_DELAY 32'h0000_0000 ;
        pci_error_data <= #`FF_DELAY 32'h0000_0000 ;
        pci_error_be <= #`FF_DELAY 4'h0 ;
        pci_error_bc <= #`FF_DELAY 4'h0 ;

        // wait for negedge - give FFs and outputs enough setup time
        @(negedge wb_clock) ;
        
        // fi