test_bench.v

PCI IP核功能实现

            // increment burst address
            current_address = current_address + 4 ;
            
            i = i + 1 ;
        end //while

        // check if whole image has been done
        if (i < 1024)
            $display("WISHBONE slave responded with error or retry to early! It didn't allow whole configuration space access!") ;
    
        // check outputs from conf space 
        // wait one clock edge for cycle to finish
        @(posedge wb_clock) ;

        // check if every output from configuration space is as it should be
        if (~serr_enable)
            $display("System error enable bit wasn't set although written one to it!") ;
        if (~perr_response)
            $display("Parity error response bit wasn't set although written one to it!") ;
        if (~pci_master_enable)
            $display("PCI master enable bit wasn't set although written one to it!") ;
        if (~memory_space_enable)
            $display("Memory space enable bit wasn't set although written one to it!") ;
        if (~io_space_enable)
            $display("I/O space enable bit wasn't set although written one to it!") ;

        if (cache_line_size_probe !== 8'hFF)
            $display("Cacheline size output didn't reflect a value written to cacheline size register!") ;
        if (latency_tim_probe !== 8'hFF)
            $display("Latency timer output didn't reflect a value written to latency timer register!") ;
        if (int_pin_probe !== 3'b001)
            $display("Interrupt pin output didn't reflect a value written to interrupt pin register!") ;

        if (pci_ba0 !== 20'hFFFF_F)
            $display("PCI base address 0 register didn't reflect a value written to it!") ;
        if (pci_ba1 !== 20'hFFFF_F)
            $display("PCI base address 1 register didn't reflect a value written to it!") ;
        if (pci_ba2 !== 20'hFFFF_F)
            $display("PCI base address 2 register didn't reflect a value written to it!") ;
        if (pci_ba3 !== 20'hFFFF_F)
            $display("PCI base address 3 register didn't reflect a value written to it!") ;
        if (pci_ba4 !== 20'hFFFF_F)
            $display("PCI base address 4 register didn't reflect a value written to it!") ;
        if (pci_ba5 !== 20'hFFFF_F)
            $display("PCI base address 5 register didn't reflect a value written to it!") ;
        if (pci_map[5:0] !== 6'b1111_11)
            $display("PCI address space mapping values didn't reflect values written to them!") ;
        if (pci_am0 !== 20'hFFFF_F)
            $display("PCI address mask 0 register didn't reflect a value written to it!") ;
        if (pci_am1 !== 20'hFFFF_F)
            $display("PCI address mask 1 register didn't reflect a value written to it!") ;
        if (pci_am2 !== 20'hFFFF_F)
            $display("PCI address mask 2 register didn't reflect a value written to it!") ;
        if (pci_am3 !== 20'hFFFF_F)
            $display("PCI address mask 3 register didn't reflect a value written to it!") ;
        if (pci_am4 !== 20'hFFFF_F)
            $display("PCI address mask 4 register didn't reflect a value written to it!") ;
        if (pci_am5 !== 20'hFFFF_F)
            $display("PCI address mask 5 register didn't reflect a value written to it!") ;
		if (pci_ta0 !== 20'hFFFF_F)
            $display("PCI translation address 0 register didn't reflect a value written to it!") ;
        if (pci_ta1 !== 20'hFFFF_F)
            $display("PCI translation address 1 register didn't reflect a value written to it!") ;
        if (pci_ta2 !== 20'hFFFF_F)
            $display("PCI translation address 2 register didn't reflect a value written to it!") ;
        if (pci_ta3 !== 20'hFFFF_F)
            $display("PCI translation address 3 register didn't reflect a value written to it!") ;
        if (pci_ta4 !== 20'hFFFF_F)
            $display("PCI translation address 4 register didn't reflect a value written to it!") ;
        if (pci_ta5 !== 20'hFFFF_F)
            $display("PCI translation address 5 register didn't reflect a value written to it!") ;
		if (pci_img_ctrl0 !== 2'b11)
            $display("PCI image control 0 register didn't reflect a value written to it!") ;
        if (pci_img_ctrl1 !== 2'b11)
            $display("PCI image control 1 register didn't reflect a value written to it!") ;
        if (pci_img_ctrl2 !== 2'b11)
            $display("PCI image control 2 register didn't reflect a value written to it!") ;
        if (pci_img_ctrl3 !== 2'b11)
            $display("PCI image control 3 register didn't reflect a value written to it!") ;
        if (pci_img_ctrl4 !== 2'b11)
            $display("PCI image control 4 register didn't reflect a value written to it!") ;
        if (pci_img_ctrl5 !== 2'b11)
            $display("PCI image control 5 register didn't reflect a value written to it!") ;

        if (~pci_error_en)
            $display("PCI error loging enable output didn't reflect a value written to it!") ;

        if (wb_ba0 !== `WB_CONFIGURATION_BASE)
            $display("WISHBONE base address 0 register didn't reflect a value of conf. space base address!") ;
        if (wb_ba1 !== 20'hFFFF_F)
            $display("WISHBONE base address 1 register didn't reflect a value written to it!") ;
        if (wb_ba2 !== 20'hFFFF_F)
            $display("WISHBONE base address 2 register didn't reflect a value written to it!") ;
        if (wb_ba3 !== 20'hFFFF_F)
            $display("WISHBONE base address 3 register didn't reflect a value written to it!") ;
        if (wb_ba4 !== 20'hFFFF_F)
            $display("WISHBONE base address 4 register didn't reflect a value written to it!") ;
        if (wb_ba5 !== 20'hFFFF_F)
            $display("WISHBONE base address 5 register didn't reflect a value written to it!") ;
        if (wb_map[5:1] !== 5'b1111_1)
            $display("WISHBONE address space mapping values didn't reflect values written to them!") ;
        if (wb_am0 !== 20'hFFFF_F)
            $display("WISHBONE address mask 0 register didn't reflect a value corresponding to 4KB size of conf. space!") ;
        if (wb_am1 !== 20'hFFFF_F)
            $display("WISHBONE address mask 1 register didn't reflect a value written to it!") ;
        if (wb_am2 !== 20'hFFFF_F)
            $display("WISHBONE address mask 2 register didn't reflect a value written to it!") ;
        if (wb_am3 !== 20'hFFFF_F)
            $display("WISHBONE address mask 3 register didn't reflect a value written to it!") ;
        if (wb_am4 !== 20'hFFFF_F)
            $display("WISHBONE address mask 4 register didn't reflect a value written to it!") ;
        if (wb_am5 !== 20'hFFFF_F)
            $display("WISHBONE address mask 5 register didn't reflect a value written to it!") ;
		if (wb_ta0 !== 20'h0000_0)
            $display("WISHBONE translation address 0 register didn't reflect a value of 0x00000!") ;
        if (wb_ta1 !== 20'hFFFF_F)
            $display("WISHBONE translation address 1 register didn't reflect a value written to it!") ;
        if (wb_ta2 !== 20'hFFFF_F)
            $display("WISHBONE translation address 2 register didn't reflect a value written to it!") ;
        if (wb_ta3 !== 20'hFFFF_F)
            $display("WISHBONE translation address 3 register didn't reflect a value written to it!") ;
        if (wb_ta4 !== 20'hFFFF_F)
            $display("WISHBONE translation address 4 register didn't reflect a value written to it!") ;
        if (wb_ta5 !== 20'hFFFF_F)
            $display("WISHBONE translation address 5 register didn't reflect a value written to it!") ;
		if (wb_img_ctrl0 !== 3'b000)
            $display("WISHBONE image control 0 register didn't reflect a value right for configuration space!") ;
        if (wb_img_ctrl1 !== 3'b111)
            $display("WISHBONE image control 1 register didn't reflect a value written to it!") ;
        if (wb_img_ctrl2 !== 3'b111)
            $display("WISHBONE image control 2 register didn't reflect a value written to it!") ;
        if (wb_img_ctrl3 !== 3'b111)
            $display("WISHBONE image control 3 register didn't reflect a value written to it!") ;
        if (wb_img_ctrl4 !== 3'b111)
            $display("WISHBONE image control 4 register didn't reflect a value written to it!") ;
        if (wb_img_ctrl5 !== 3'b111)
            $display("WISHBONE image control 5 register didn't reflect a value written to it!") ;

        if (~wb_error_en)
            $display("WB error logging enable output didn't reflect a value written to it!") ;
		if ({8'h00, config_addr} !== 32'h00FF_FFFD)
            $display("Configuration cycle address output didn't reflect a value written to register!") ;
        if (~icr_soft_res)
            $display("Software reset output didn't reflect a value written to it!") ;
        if (~serr_int_en)
            $display("System error interrupt enable output didn't reflect a value written to it!") ;
        if (~perr_int_en)
            $display("Parity error interrupt enable output didn't reflect a value written to it!") ;
        if (~error_int_en)
            $display("WB error interrupt enable output didn't reflect a value written to it!") ;        
        if (~int_prop_en)
            $display("Interrupt propagation interrupt enable output didn't reflect a value written to it!") ;        
        
        // do actual reads from conf_space and compare read values with expected ones
        // apply start address
        current_address = {`WB_CONFIGURATION_BASE, 12'h000} ;

        // loop for performing 4KB (1Kx4) of reads - whole configuration space address range
        i = 0 ;
        result = 3'b000 ;
        while ( (i < 1024) && (result[1:0] == 2'b00) )
        begin
            // check if this is configuration cycle or interrupt acknowledge generation access - skip them by inserting wait states
            if ( (current_address[11:0] == `CNF_DATA_ADDR) || (current_address[11:0] == `INT_ACK_ADDR) )
                read_select = 4'hx ;
            else
                read_select = 4'hf ;
            
            // do a write
            wishbone_master.blkrd( current_address, read_select, 1'b0, (i == 0), ((i + 1) == 1024), {result, read_data} ) ;
            
            // check response
            if (result[2]) // transfer acknowledged
            begin
                // check what address was currently read and see, if data is OK
                case (current_address)
                    // type0 header test
                    { `WB_CONFIGURATION_BASE, 12'h000 }:if (read_data !== {`HEADER_DEVICE_ID, `HEADER_VENDOR_ID})
                                                            display_warning(current_address, {`HEADER_DEVICE_ID, `HEADER_VENDOR_ID}, read_data) ;

                    { `WB_CONFIGURATION_BASE, 12'h004 }:if (read_data !== header_cs)
                                                            display_warning(current_address, header_cs, read_data) ;

                    { `WB_CONFIGURATION_BASE, 12'h008 }:`ifdef HOST
                                                            if (read_data !== {24'h06_00_00, `HEADER_REVISION_ID} )
                                                                display_warning(current_address, {24'h06_00_00, `HEADER_REVISION_ID}, read_data) ;
                                                        `else
                                                            if (read_data !== {24'h06_80_00, `HEADER_REVISION_ID} )
                                                                display_warning(current_address, {24'h06_80_00, `HEADER_REVISION_ID}, read_data) ;
                                                        `endif

                    { `WB_CONFIGURATION_BASE, 12'h00C }:if (read_data !== 32'h0000_FFFF)
                                                            display_warning(current_address, 32'h0000_FFFF, read_data) ;

                    { `WB_CONFIGURATION_BASE, 12'h010 }, 
                    { `WB_CONFIGURATION_BASE, 12'h014 }, 
                    { `WB_CONFIGURATION_BASE, 12'h018 }, 
                    { `WB_CONFIGURATION_BASE, 12'h01C }, 
                    { `WB_CONFIGURATION_BASE, 12'h020 }, 
                    { `WB_CONFIGURATION_BASE, 12'h024 }:if (read_data !== 32'hFFFF_F001)
                                                            display_warning(current_address, 32'hFFFF_F001, read_data) ;

                    { `WB_CONFIGURATION_BASE, 12'h03C }:if (read_data !== 32'h1A08_01FF)
                                                            display_warning(current_address, 32'h1A08_01FF, read_data) ;

                    // all pci image control registers must return same value
                    { `WB_CONFIGURATION_BASE, `P_IMG_CTRL0_ADDR }, 
                    { `WB_CONFIGURATION_BASE, `P_IMG_CTRL1_ADDR }, 
                    { `WB_CONFIGURATION_BASE, `P_IMG_CTRL2_ADDR }, 
                    { `WB_CONFIGURATION_BASE, `P_IMG_CTRL3_ADDR }, 
                    { `WB_CONFIGURATION_BASE, `P_IMG_CTRL4_ADDR }, 
                    { `WB_CONFIGURATION_BASE, `P_IMG_CTRL5_ADDR }:  if (read_data !== 32'h0000_0006)
                                                                        display_warning(current_address, 32'h0000_0006, read_data) ;
                                                                            
                    // all pci base address registers must return same value
                    { `WB_CONFIGURATION_BASE, `P_BA0_ADDR },				
                    { `WB_CONFIGURATION_BASE, `P_BA1_ADDR },				
                    { `WB_CONFIGURATION_BASE, `P_BA2_ADDR },				
                    { `WB_CONFIGURATION_BASE, `P_BA3_ADDR },				
                    { `WB_CONFIGURATION_BASE, `P_BA4_ADDR },				
                    { `WB_CONFIGURATION_BASE, `P_BA5_ADDR }:if (read_data !== 32'hFFFF_F001)
                                                                display_warning(current_address, 32'hFFFF_F001, read_data) ;    

                    // all pci address mask registers must return same value
                    { `WB_CONFIGURATION_BASE, `P_AM0_ADDR },				
                    { `WB_CONFIGURATION_BASE, `P_AM1_ADDR },				
                    { `WB_CONFIGURATION_BASE, `P_AM2_ADDR },				
                    { `WB_CONFIGURATION_BASE, `P_AM3_ADDR },				
                    { `WB_CONFIGURATION_BASE, `P_AM4_ADDR },				
        			{ `WB_CONFIGURATION_BASE, `P_AM5_ADDR }:if (read_data !== 32'hFFFF_F000)
                                                                display_warning(current_address, 32'hFFFF_F000, read_data) ;    

                    // all pci translation address registers must return same value            
                    { `WB_CONFIGURATION_BASE, `P_TA0_ADDR },
				    { `WB_CONFIGURATION_BASE, `P_TA1_ADDR },
                    { `WB_CONFIGURATION_BASE, `P_TA2_ADDR },
                    { `WB_CONFIGURATION_BASE, `P_TA3_ADDR },
                    { `WB_CONFIGURATION_BASE, `P_TA4_ADDR },
				    { `WB_CONFIGURATION_BASE, `P_TA5_ADDR }:if (read_data !== 32'hFFFF_F000)
                                                                display_warning(current_address, 32'hFFFF_F000, read_data) ;    
                    
                    { `WB_CONFIGURATION_BASE, `P_ERR_CS_ADDR }: if (read_data !== 32'h0000_0001)
                                                                    display_warning(current_address, 32'h0000_0001, read_data) ;    
                    
                    { `WB_CONFIGURATION_BASE, `P_ERR_ADDR_ADDR }:   if (read_data !== 32'h0000_0000)
                                                                        display_warning(current_address, 32'h0000_0000, read_data) ;    
                    
                    { `WB_CONFIGURATION_BASE, `P_ERR_DATA_ADDR }:   if (read_data !== 32'h0000_0000)
                                                                        display_warning(current_address, 32'h0000_0000, read_data) ;       

                    { `WB_CONFIGURATION_BASE, `WB_CONF_SPC_BAR_ADDR }:  if (read_data !== {`WB_CONFIGURATION_BASE, 12'h000})
                                                                            display_warning(current_address, {`WB_CONFIGURATION_BASE, 12'h000}, read_data) ;       

                    // all WISHBONE image configuration registers must return same value
				    { `WB_CONFIGURATION_BASE, `W_IMG_CTRL1_ADDR },
				    { `WB_CONFIGURATION_BASE, `W_IMG_CTRL2_ADDR },		
                    { `WB_CONFIGURATION_BASE, `W_IMG_CTRL3_ADDR },		
			        { `WB_CONFIGURATION_BASE, `W_IMG_CTRL4_ADDR },		
                    { `WB_CONFIGURATION_BASE, `W_IMG_CTRL5_ADDR }:  if (read_data !== 32'h0000_0007)
                                                                        display_warning(current_address, 32'h0000_0007, read_data) ;      
                    
                    // all WISHBONE base address registers must return same value
                    { `WB_CONFIGURATION_BASE, `W_BA1_ADDR },
                    { `WB_CONFIGURATION_BASE, `W_BA2_ADDR },
                    { `WB_CONFIGURATION_BASE, `W_BA3_ADDR },
                    { `WB_CONFIGURATION_BASE, `W_BA4_ADDR },
                    { `WB_CONFIGURATION_BASE, `W_BA5_ADDR }:if (read_data !== 32'hFFFF_F001)
                                                                display_warning(current_address, 32'hFFFF_F001, read_data) ;    

                    // all WISHBONE address mask registers must return same value
                    { `WB_CONFIGURATION_BASE, `W_AM1_ADDR },
                    { `WB_CONFIGURATION_BASE, `W_AM2_ADDR },
				    { `WB_CONFIGURATION_BASE, `W_AM3_ADDR },
                    { `WB_CONFIGURATION_BASE, `W_AM4_ADDR },
                    { `WB_CONFIGURATION_BASE, `W_AM5_ADDR }:if (read_data !== 32'hFFFF_F000)
                                                                display_warning(current_address, 32'hFFFF_F000, read_data) ;    

                    // all WISHBONE translation address registers must return same value
                    { `WB_CONFIGURATION_BASE, `W_TA1_ADDR },