test_bench.v

PCI IP核功能实现

                                // inputs to status register of the PCI header      
					            .perr_in             (perr_set),
                                .serr_in             (serr_set),
                                .master_abort_recv   (master_abort_recv),
                                .target_abort_recv   (target_abort_recv),
                                .target_abort_set    (target_abort_set),
                                .master_data_par_err (master_data_par_err),
                                // output from cache_line_size, latency timer and   
                                // r_interrupt_pin register of the PCI header       
					            .cache_line_size     (cache_line_size_probe),
                                .latency_tim         (latency_tim_probe),
                                .int_pin             (int_pin_probe),
                                // output from all pci IMAGE registers
					            .pci_base_addr0 (pci_ba0),
                                .pci_base_addr1 (pci_ba1),
                                .pci_base_addr2 (pci_ba2),
                                .pci_base_addr3 (pci_ba3),
                                .pci_base_addr4 (pci_ba4),
                                .pci_base_addr5 (pci_ba5),
					            .pci_memory_io0 (pci_map[0]),
                                .pci_memory_io1 (pci_map[1]),
                                .pci_memory_io2 (pci_map[2]),
                                .pci_memory_io3 (pci_map[3]),
                                .pci_memory_io4 (pci_map[4]),
                                .pci_memory_io5 (pci_map[5]),
					            .pci_addr_mask0 (pci_am0),
                                .pci_addr_mask1 (pci_am1),
                                .pci_addr_mask2 (pci_am2),
                                .pci_addr_mask3 (pci_am3),
                                .pci_addr_mask4 (pci_am4),
                                .pci_addr_mask5 (pci_am5),
					            .pci_tran_addr0 (pci_ta0),
                                .pci_tran_addr1 (pci_ta1),
                                .pci_tran_addr2 (pci_ta2),
                                .pci_tran_addr3 (pci_ta3),
                                .pci_tran_addr4 (pci_ta4),
                                .pci_tran_addr5 (pci_ta5),
					            .pci_img_ctrl0  (pci_img_ctrl0),
                                .pci_img_ctrl1  (pci_img_ctrl1),
                                .pci_img_ctrl2  (pci_img_ctrl2),
                                .pci_img_ctrl3  (pci_img_ctrl3),
                                .pci_img_ctrl4  (pci_img_ctrl4),
                                .pci_img_ctrl5  (pci_img_ctrl5),
                                // input to pci error control and status register, 
                                // error address and error data registers
					            .pci_error_be      (pci_error_be),
                                .pci_error_bc      (pci_error_bc),
                                .pci_error_rty_exp (pci_error_rty_exp),
                                .pci_error_sig     (pci_error_sig),
                                .pci_error_addr    (pci_error_addr),
                                .pci_error_data    (pci_error_data),
                                .pci_error_rty_exp_set (pci_error_rty_exp_set),
                                // output from pci error control and status register
					            .pci_error_en     (pci_error_en),
                                // output from all wishbone IMAGE registers                                                                                          
					            .wb_base_addr0    (wb_ba0),
                                .wb_base_addr1    (wb_ba1),
                                .wb_base_addr2    (wb_ba2),
                                .wb_base_addr3    (wb_ba3),
                                .wb_base_addr4    (wb_ba4),
                                .wb_base_addr5    (wb_ba5),
					            .wb_memory_io0    (),
                                .wb_memory_io1    (wb_map[1]),
                                .wb_memory_io2    (wb_map[2]),
                                .wb_memory_io3    (wb_map[3]),
                                .wb_memory_io4    (wb_map[4]),
                                .wb_memory_io5    (wb_map[5]),
					            .wb_addr_mask0    (wb_am0),
                                .wb_addr_mask1    (wb_am1),
                                .wb_addr_mask2    (wb_am2),
                                .wb_addr_mask3    (wb_am3),
                                .wb_addr_mask4    (wb_am4),
                                .wb_addr_mask5    (wb_am5),
					            .wb_tran_addr0    (wb_ta0),
                                .wb_tran_addr1    (wb_ta1),
                                .wb_tran_addr2    (wb_ta2),
                                .wb_tran_addr3    (wb_ta3),
                                .wb_tran_addr4    (wb_ta4),
                                .wb_tran_addr5    (wb_ta5),
					            .wb_img_ctrl0     (wb_img_ctrl0),
                                .wb_img_ctrl1     (wb_img_ctrl1),
                                .wb_img_ctrl2     (wb_img_ctrl2),
                                .wb_img_ctrl3     (wb_img_ctrl3),
                                .wb_img_ctrl4     (wb_img_ctrl4),
                                .wb_img_ctrl5     (wb_img_ctrl5),
                                // input to wb error control and status register,
                                // error address and error data registers        (),
					            .wb_error_be      (wb_error_be),
                                .wb_error_bc      (wb_error_bc),
                                .wb_error_rty_exp (wb_error_rty_exp),
                                .wb_error_es      (wb_error_es),
                                .wb_error_sig     (wb_error_sig),
                                .wb_error_addr    (wb_error_addr),
                                .wb_error_data    (wb_error_data),
                                .wb_error_rty_exp_set (wb_error_rty_exp_set), 
                                // output from wb error control and status register
					            .wb_error_en      (wb_error_en),
                                // output from conf. cycle generation register 
                                // (sddress) & int. control register
					            .config_addr  (config_addr),
                                .icr_soft_res (icr_soft_res),
                                .serr_int_en  (serr_int_en), 
                                .perr_int_en  (perr_int_en),
                                .error_int_en (error_int_en),
                                .int_prop_en  (int_prop_en),
                                // input to interrupt status register
					            .isr_int_prop (isr_int_prop),
                                .isr_err_int  (isr_err_int), 
                                .isr_par_err_int (isr_par_err_int),
                                .isr_sys_err_int (isr_sys_err_int),
                                .pci_error_sig_set (pci_error_sig_set),
                                .wb_error_sig_set (wb_error_sig_set)
                            ) ;

integer temp_index ;
// initial state
initial
begin
    // guest implementation not supported in this testbench
    `ifdef GUEST
        $display("GUEST implementation not supported in this testbench") ;
        $finish ;
    `endif
    // clocks
    wb_clock <= 1'b0 ;
    pci_clock <= 1'b1 ;
      
    // read enable for wbw_fifo
    wbw_renable <= 1'b0 ;
    
    // write enable for wbr_fifo
    wbr_wenable <= 1'b0 ;
    
    // byte enable input to wbr fifo
    wbr_be_in <= 4'hF ;
    
    // control input to wbr fifo
    wbr_control_in <= 4'h0 ;
    
    // pciw fifo empty indicator
    pciw_empty <= 1'b1 ;
    
    // pci side delayed read completion pending flag
    pci_drcomp_pending <= 1'b0 ;
    
    // lock variable
    wbs_lock  <= 1'b0 ;
    
    // various inputs to configuration space are initialized to 0s
    perr_set <= 1'b0 ;
    serr_set <= 1'b0 ; 
    master_abort_recv <= 1'b0 ; 
    target_abort_recv <= 1'b0 ; 
    target_abort_set <= 1'b0 ; 
    master_data_par_err <= 1'b0 ;
    pci_error_sig <= 1'b0 ;
    wb_error_rty_exp <= 1'b0 ;
    wb_error_es <= 1'b0 ;
    wb_error_sig <= 1'b0 ;

    isr_int_prop <= 1'b0 ;
    isr_err_int <= 1'b0  ;
    isr_par_err_int <= 1'b0 ;
    isr_sys_err_int <= 1'b0 ;

    pci_error_rty_exp <= 1'b0 ;

    pci_error_be <= 4'h0 ;
    pci_error_bc <= 4'h0 ;
    pci_error_addr <= 32'h00000000 ;
    pci_error_data <= 32'h00000000 ;

    wb_error_be <= 4'h0 ;
    wb_error_bc <= 4'h0 ;
    wb_error_addr <= 32'h00000000 ;
    wb_error_data <= 32'h00000000 ;

    // error terminate variable for delayed reads
    del_error_signal <= 1'b0 ;

    error_terminate  <= 1'b0 ;

    // read completion signal
    del_comp_done <= 1'b0 ;

    // retry counter expired variable
    del_rty_exp <= 1'b0 ;

    // fill write memories with random data
    for( temp_index = 0; temp_index <=1023; temp_index = temp_index + 1 )
    begin
        wmem_data[temp_index[9:0]] = $random ;
        wio_data[temp_index[9:0]]  = $random ;
    end

    // run tests
    run_tests ;
    $stop ;

end //initial

// clocks generation
always 
begin
   #`Tpci pci_clock = ~pci_clock ;
end

always 
begin
   #`Twb wb_clock = ~wb_clock ;
end

task run_tests ;
begin
    // first - reset logic
    do_reset ;
    conf_space_test ;
    wb_error_log_test ;
    pci_error_log_test ;
    pci_status_reg_test ;
    interrupt_status_reg_test ;
    image_testing ;
    conf_cycle_test ;
    iack_cycle_test ;
    error_termination_test ;
    dlyd_req_rty_exp_test ;
    force_write_with_read_test ;
end
endtask //run_tests

// task for warning displays
task display_warning;
    input [31:0] error_address ;
    input [31:0] expected_data ;
    input [31:0] actual ;
begin
    $display("Read from address %h produced wrong result! \nExpected value was %h\tread value was %h!", error_address, expected_data, actual) ;
end
endtask // display warning

// reset task
task do_reset;
begin
    reset <= 1'b0 ;
    #1 reset <= 1'b1 ;
    #100 reset <= 1'b0 ;
end
endtask

// constant for control and status register check
wire [31:0] header_cs = { 10'b0000_0010_00, `HEADER_66MHz, 5'b0_0000, 16'h0147 };
task conf_space_test ;
    reg [31:0] current_address ;
    integer i ;
    reg [2:0] result ;
    reg [31:0] write_data ;
    reg [31:0] read_data ;
    reg [3:0] read_select ;
    
    begin 
        $display("Starting configuration space test") ;

        // apply start address
        current_address = {`WB_CONFIGURATION_BASE, 12'h000} ;

        // loop for performing 4KB (1Kx4) of writes - whole configuration space address range
        i = 0 ;
        result = 3'b000 ;
        while ( (i < 1024) && (result[1:0] == 2'b00) )
        begin
            // check if this is configuration cycle generation access - skip it by inserting wait state
            if ( current_address[11:0] == `CNF_DATA_ADDR )
                write_data = 32'hxxxx_xxxx ;
            else
                write_data = 32'hffff_ffff ;
            
            // do a write
            wishbone_master.blkwr( current_address, write_data, 4'hF, 1'b0, (i == 0), ((i + 1) == 1024), result ) ;