test_bench.v

PCI IP核功能实现

                        .wb_clock_in              (wb_clock) ,
                        .reset_in                 (reset) ,
                        .wb_hit_in                (hit) ,
                        .wb_conf_hit_in           (conf_hit) ,
                        .wb_map_in                (wb_map) ,
                        .wb_pref_en_in            (wb_pref) ,
                        .wb_mrl_en_in             (wb_mrl) ,
                        .wb_addr_in               (address) ,
                        .del_bc_in                (del_bc) ,
                        .wb_del_req_pending_in    (del_req) ,
                        .wb_del_comp_pending_in   (del_comp) ,
                        .pci_drcomp_pending_in    (pci_drcomp_pending) ,
                        .del_bc_out               (del_bc_probe) ,
                        .del_req_out              (del_req_probe) ,
                        .del_done_out             (del_done_probe) ,
                       	.del_burst_out            (del_burst_probe) ,
                        .del_write_out            (del_write_probe),
                        .del_write_in             (del_write),
                        .del_error_in             (del_error),
                        .wb_del_addr_in           (del_addr) ,
                        .wb_del_be_in             (del_be) ,
                        .wb_conf_offset_out       (conf_offset_probe) ,
                        .wb_conf_renable_out      (conf_renable_probe) ,
                        .wb_conf_wenable_out      (conf_wenable_probe) ,
                        .wb_conf_be_out           (conf_be_probe) ,
                        .wb_conf_data_in          (conf_data) ,
                        .wb_conf_data_out         (conf_data_probe) ,
                        .wb_data_out              (image_data) ,
                        .wb_cbe_out               (image_cbe) ,
                        .wbw_fifo_wenable_out     (wbw_wenable) ,
                        .wbw_fifo_control_out     (wbw_control) ,
                        .wbw_fifo_almost_full_in  (wbw_almost_full) ,
                        .wbw_fifo_full_in         (wbw_full) ,
                        .wbr_fifo_renable_out     (wbr_renable) ,
                        .wbr_fifo_be_in           (wbr_be) ,
                        .wbr_fifo_data_in         (wbr_data) ,
                        .wbr_fifo_control_in      (wbr_control) ,
                        .wbr_fifo_flush_out       (wbs_wbr_flush) ,
                        .wbr_fifo_almost_empty_in (wbr_almost_empty), 
                        .wbr_fifo_empty_in        (wbr_empty),     
                        .pciw_fifo_empty_in       (pciw_empty),
                        .wbs_lock_in              (wbs_lock),
                        .del_in_progress_out      (del_in_progress),
                        .ccyc_addr_in             ({8'h00, config_addr}),
                        .CYC_I                    (cyc),
                        .STB_I                    (stb),
                        .WE_I                     (we),
                        .SEL_I                    (sel),
                        .SDATA_I                  (sdat_i),
                        .SDATA_O                  (sdat_o),
                        .ACK_O                    (ack),
                        .RTY_O                    (rty),
                        .ERR_O                    (err),
                        .CAB_I                    (cab)
                       );

// behavioral WISHBONE master instantiation
WB_MASTER32 wishbone_master(
                            .CLK_I(wb_clock), 
                            .RST_I(reset), 
                            .TAG_I(4'b0), 
                            .TAG_O(),
		                    .ACK_I(ack), 
                            .ADR_O(addr_o), 
                            .CYC_O(cyc), 
                            .DAT_I(sdat_o), 
                            .DAT_O(sdat_i), 
                            .ERR_I(err), 
                            .RTY_I(rty), 
                            .SEL_O(sel), 
                            .STB_O(stb), 
                            .WE_O (we),
                            .CAB_O(cab)
                           ) ;

// WBW_FIFO and WBR_FIFO instantiation
WBW_WBR_FIFOS fifos(
                    .wb_clock_in               (wb_clock),
                    .pci_clock_in              (pci_clock),
                    .reset_in                  (reset),
                    .wbw_wenable_in            (wbw_wenable),
                    .wbw_addr_data_in          (image_data),
                    .wbw_cbe_in                (image_cbe),
                    .wbw_control_in            (wbw_control),         
                    .wbw_renable_in            (wbw_renable),
                    .wbw_addr_data_out         (wbw_data_probe),
                    .wbw_cbe_out               (wbw_cbe_probe),
                    .wbw_control_out           (wbw_control_probe),          
                    .wbw_flush_in              (1'b0),
                    .wbw_almost_full_out       (wbw_almost_full),
                    .wbw_full_out              (wbw_full),
                    .wbw_almost_empty_out      (wbw_almost_empty_probe),
                    .wbw_empty_out             (wbw_empty_probe),
                    .wbw_transaction_ready_out (wbw_transaction_probe),
                    .wbr_wenable_in            (wbr_wenable), 
                    .wbr_data_in               (wbr_data_in),
                    .wbr_be_in                 (wbr_be_in),
                    .wbr_control_in            (wbr_control_in),         
                    .wbr_renable_in            (wbr_renable),
                    .wbr_data_out              (wbr_data),
                    .wbr_be_out                (wbr_be),
                    .wbr_control_out           (wbr_control),          
                    .wbr_flush_in              (wbr_flush),
                    .wbr_almost_full_out       (wbr_almost_full_probe),
                    .wbr_full_out              (wbr_full_probe),
                    .wbr_almost_empty_out      (wbr_almost_empty),
                    .wbr_empty_out             (wbr_empty),
                    .wbr_transaction_ready_out (wbr_transaction_probe)
                   ) ;

// bus monitor instantiation
WB_BUS_MON wishbone_monitor(
                            .CLK_I  (wb_clock),
                            .RST_I  (reset),
		                    .ACK_I  (ack),
                            .ADDR_O (addr_o), 
                            .CYC_O  (cyc),
                            .DAT_I  (sdat_o),
                            .DAT_O  (sdat_i),
                            .ERR_I  (err),
                            .RTY_I  (rty),
                            .SEL_O  (sel),
                            .STB_O  (stb),
                            .WE_O   (we),
                            .TAG_I  (1'b0),
                            .TAG_O  (1'b0),
                            .CAB_O  (cab)
                           ) ;

// address outputs from decoders
wire [31:0] conf_addr ;
wire [31:0] img_addr1 ;
wire [31:0] img_addr2 ;
wire [31:0] img_addr3 ;
wire [31:0] img_addr4 ;
wire [31:0] img_addr5 ;

// input wires to decoders
wire [19:0] wb_ba0, wb_ba1, wb_ba2, wb_ba3, wb_ba4, wb_ba5 ; 
wire [19:0] wb_am0, wb_am1, wb_am2, wb_am3, wb_am4, wb_am5 ; 
wire [19:0] wb_ta0, wb_ta1, wb_ta2, wb_ta3, wb_ta4, wb_ta5 ; 

//address decoder instantiation
DECODER dec1(
                .hit       (hit[0]),
                .addr_out  (img_addr1),
                .addr_in   (addr_o),
                .base_addr (wb_ba1),
                .mask_addr (wb_am1),
                .tran_addr (wb_ta1),
                .at_en     (wb_img_ctrl1[2])
            ) ;

DECODER dec2(
                .hit       (hit[1]),
                .addr_out  (img_addr2),
                .addr_in   (addr_o),
                .base_addr (wb_ba2),
                .mask_addr (wb_am2),
                .tran_addr (wb_ta2),
                .at_en     (wb_img_ctrl2[2])
            ) ;

DECODER dec3(
                .hit       (hit[2]),
                .addr_out  (img_addr3),
                .addr_in   (addr_o),
                .base_addr (wb_ba3),
                .mask_addr (wb_am3),
                .tran_addr (wb_ta3),
                .at_en     (wb_img_ctrl3[2])
            ) ;

DECODER dec4(
                .hit       (hit[3]),
                .addr_out  (img_addr4),
                .addr_in   (addr_o),
                .base_addr (wb_ba4),
                .mask_addr (wb_am4),
                .tran_addr (wb_ta4),
                .at_en     (wb_img_ctrl4[2])
            ) ;

DECODER dec5(
                .hit       (hit[4]),
                .addr_out  (img_addr5),
                .addr_in   (addr_o),
                .base_addr (wb_ba5),
                .mask_addr (wb_am5),
                .tran_addr (wb_ta5),
                .at_en     (wb_img_ctrl5[2])
            ) ;

// address mux
always@(hit or conf_hit or img_addr1 or img_addr2 or img_addr3 or img_addr4 or img_addr5 or conf_addr)
begin
    case(hit)
        5'h01:address <= img_addr1 ;    
        5'h02:address <= img_addr2 ;
        5'h04:address <= img_addr3 ;
        5'h08:address <= img_addr4 ;
        5'h10:address <= img_addr5 ;
        default: address <= conf_addr ;
    endcase
end

// configuration space decoder
DECODER dec0(
                .hit       (conf_hit),
                .addr_out  (conf_addr),
                .addr_in   (addr_o),
                .base_addr (wb_ba0),
                .mask_addr (wb_am0),
                .tran_addr (wb_ta0),
                .at_en     (wb_img_ctrl0[2])
            ) ;

// delayed transaction logic instantiation
DELAYED_SYNC del_sync  (
                                .reset_in             (reset),
                                .req_clk_in           (wb_clock),
                                .comp_clk_in          (pci_clock),
                                .req_in               (del_req_probe),
                                .comp_in              (del_comp_done),
                                .done_in              (del_done_probe),
                                .in_progress_in       (del_in_progress),
                                .comp_req_pending_out (pci_req),
                                .req_req_pending_out  (del_req),
                                .req_comp_pending_out (del_comp),
                                .addr_in              (image_data),
                                .be_in                (conf_be_probe),
                                .addr_out             (del_addr),
                                .be_out               (del_be),
                                .we_in                (del_write_probe),
                                .we_out               (del_write),
                                .bc_in                (del_bc_probe),
                                .bc_out               (del_bc),
                                .status_in            (del_error_signal),
                                .status_out           (del_error),
                                .comp_flush_out       (delayed_sync_wbr_flush),
                                .burst_in             (del_burst_probe),
                                .burst_out            (read_in_burst),
                                .retry_expired_in     (del_rty_exp)
                            );

wire [31:0] del_write_data ;
DELAYED_WRITE_REG delayed_write_data
(
	.reset_in       (reset),
	.req_clk_in     (wb_clock),
	.comp_wdata_out (del_write_data),
	.req_we_in      (del_req_probe && del_write_probe),
	.req_wdata_in   (conf_data_probe)
);




CONF_SPACE configuration    (	
                                .w_conf_address_in   (conf_offset_probe),
                                .w_conf_data_in      (conf_data_probe),
                                .w_conf_data_out     (conf_data),
                                .r_conf_address_in   (pci_conf_raddr),
                                .r_conf_data_out     (pci_conf_data_probe),
					            .w_we                (conf_wenable_probe),
                                .w_re                (conf_renable_probe),
                                .r_re                (pci_conf_renable),
                                .w_byte_en           (~conf_be_probe),
                                .conf_hit            (conf_hit),
                                .w_clock             (wb_clock),
                                .reset               (reset),
                                .pci_clk             (pci_clock),
                                .wb_clk              (wb_clock),
                                // outputs from command register of the PCI header  
					            .serr_enable         (serr_enable),
                                .perr_response       (perr_response),
                                .pci_master_enable   (pci_master_enable),
                                .memory_space_enable (memory_space_enable),
                                .io_space_enable     (io_space_enable),