wbw_wbr_fifos.v

PCI IP核功能实现

                wbr_write_performed <= #`FF_DELAY 1'b0 ;
            else 
                wbr_write_performed <= #`FF_DELAY wbr_wallow ;
        end

        /*-----------------------------------------------------------------------------------------------------------
        Additional register storing actual WBW read address. It must be applied to port B during turnaround cycle
        -----------------------------------------------------------------------------------------------------------*/
        reg [(WBW_ADDR_LENGTH - 1):0] wbw_raddr_0 ;

        always@(posedge pci_clock_in or posedge wbw_clear)
        begin
            if (wbw_clear)
                wbw_raddr_0 <= #`FF_DELAY {WBW_ADDR_LENGTH{1'b0}} ;
            else
                if(wbw_rallow)
                    wbw_raddr_0 <= #`FF_DELAY wbw_raddr ;
        end 
        
        wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr_calc = wbr_write_performed ? wbw_raddr_0 : wbw_raddr ;

        /*-----------------------------------------------------------------------------------------------------------
        Additional register storing actual WBR read address. It must be applied to port A during turnaround cycle
        -----------------------------------------------------------------------------------------------------------*/
        reg [(WBR_ADDR_LENGTH - 1):0] wbr_raddr_0 ;

        always@(posedge wb_clock_in or posedge wbr_clear)
        begin
            if(wbr_clear)
                wbr_raddr_0 <= #`FF_DELAY {WBR_ADDR_LENGTH{1'b0}} ;
            else
                if(wbr_rallow)
                    wbr_raddr_0 <= #`FF_DELAY wbr_raddr ;
        end 
    
        wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr_calc = wbw_write_performed ? wbr_raddr_0 : wbr_raddr ;
    
        /*-----------------------------------------------------------------------------------------------------------
        Port A and B enables
        -----------------------------------------------------------------------------------------------------------*/
        wire portA_enable = wbw_wallow || wbr_rallow || wbr_empty || wbw_write_performed ;
        wire portB_enable = wbr_wallow || wbw_rallow || wbw_empty || wbr_write_performed ;

        /*-----------------------------------------------------------------------------------------------------------
        Port A address generation for block SelectRam+ in SpartanII or Virtex
        Port A is clocked by WISHBONE clock, DIA is input for wbw_fifo, DOA is output for wbr_fifo. Address is multiplexed
        between two values.
        Address multiplexing:
        wbw_wenable == 1 => ADDRA = wbw_waddr (write pointer of WBW_FIFO)
        else                ADDRA = wbr_raddr (read pointer of WBR_FIFO)
        -----------------------------------------------------------------------------------------------------------*/
        wire [7:0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr_calc} ;
    
        /*-----------------------------------------------------------------------------------------------------------
        Port B address generation for block SelectRam+ in SpartanII or Virtex
        Port B is clocked by PCI clock, DIB is input for wbr_fifo, DOB is output for wbw_fifo. Address is multiplexed
        between two values.
        Address multiplexing:
        wbr_wenable == 1 => ADDRB = wbr_waddr (write pointer of WBR_FIFO)
        else                ADDRB = wbw_raddr (read pointer of WBW_FIFO)
        -----------------------------------------------------------------------------------------------------------*/
        wire [7:0] portB_addr = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr_calc} ;
    
        // Block SelectRAM+ cells instantiation
        RAMB4_S16_S16 dpram16_1 (.ADDRA(portA_addr), .DIA(wbw_addr_data_in[15:0]), 
                                 .ENA(portA_enable), .RSTA(reset_in),
                                 .CLKA(wb_clock_in), .WEA(wbw_wallow), 
                                 .DOA(wbr_data_out[15:0]),
                                 .ADDRB(portB_addr), .DIB(wbr_data_in[15:0]), 
                                 .ENB(portB_enable), .RSTB(reset_in),
                                 .CLKB(pci_clock_in), .WEB(wbr_wallow), 
                                 .DOB(wbw_addr_data_out[15:0])) ;

        RAMB4_S16_S16 dpram16_2 (.ADDRA(portA_addr), .DIA(wbw_addr_data_in[31:16]), 
                                 .ENA(portA_enable), .RSTA(reset_in),
                                 .CLKA(wb_clock_in), .WEA(wbw_wallow), 
                                 .DOA(wbr_data_out[31:16]),
                                 .ADDRB(portB_addr), .DIB(wbr_data_in[31:16]), 
                                 .ENB(portB_enable), .RSTB(reset_in),
                                 .CLKB(pci_clock_in), .WEB(wbr_wallow), 
                                 .DOB(wbw_addr_data_out[31:16])) ;
    
        RAMB4_S16_S16 dpram16_3 (.ADDRA(portA_addr), .DIA({wbw_control_in, 8'h00, wbw_cbe_in}), 
                                 .ENA(portA_enable), .RSTA(reset_in),
                                 .CLKA(wb_clock_in), .WEA(wbw_wallow), 
                                 .DOA(dpram3_portA_output),
                                 .ADDRB(portB_addr), .DIB({wbr_control_in, 8'h00, wbr_be_in}), 
                                 .ENB(portB_enable), .RSTB(reset_in),
                                 .CLKB(pci_clock_in), .WEB(wbr_wallow), 
                                 .DOB(dpram3_portB_output)) ;
    `endif
    
    
    
    

`else
    wire [39:0] wbw_ram_data_out ;
    wire [39:0] wbw_ram_data_in = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
    wire [39:0] wbr_ram_data_in = {wbr_control_in, wbr_be_in, wbr_data_in} ;
    wire [39:0] wbr_ram_data_out ;
    assign wbw_control_out   = wbw_ram_data_out[39:36] ;
    assign wbw_cbe_out       = wbw_ram_data_out[35:32] ;
    assign wbw_addr_data_out = wbw_ram_data_out [31:0] ;
    
    assign wbr_control_out   = wbr_ram_data_out[39:36] ;
    assign wbr_be_out        = wbr_ram_data_out[35:32] ;
    assign wbr_data_out      = wbr_ram_data_out [31:0] ;
    
    `ifdef SYNCHRONOUS
    /*-----------------------------------------------------------------------------------------------------------
    ASIC memory primitives will be added here in the near future - currently there is only some generic, 
    behavioral dual port ram here 
    -----------------------------------------------------------------------------------------------------------*/

    wire wbw_read_enable = wbw_rallow || wbw_empty ;
    wire wbr_read_enable = wbr_rallow || wbr_empty ;

    DP_SRAM #(WBW_ADDR_LENGTH, WBW_DEPTH) wbw_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .rclock_in(pci_clock_in), .data_in(wbw_ram_data_in), 
                    .raddr_in(wbw_raddr), .waddr_in(wbw_waddr), .data_out(wbw_ram_data_out), .renable_in(wbw_read_enable), .wenable_in(wbw_wallow));
    
    DP_SRAM #(WBR_ADDR_LENGTH, WBR_DEPTH) wbr_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .rclock_in(wb_clock_in), .data_in(wbr_ram_data_in),
                    .raddr_in(wbr_raddr), .waddr_in(wbr_waddr), .data_out(wbr_ram_data_out), .renable_in(wbr_read_enable), .wenable_in(wbr_wallow));
    
    `else //ASYNCHRONOUS RAM
        DP_ASYNC_RAM #(WBW_ADDR_LENGTH, WBW_DEPTH) wbw_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .data_in(wbw_ram_data_in), 
                    .raddr_in(wbw_raddr), .waddr_in(wbw_waddr), .data_out(wbw_ram_data_out), .wenable_in(wbw_wallow));
    
        DP_ASYNC_RAM #(WBR_ADDR_LENGTH, WBR_DEPTH) wbr_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .data_in(wbr_ram_data_in),
                    .raddr_in(wbr_raddr), .waddr_in(wbr_waddr), .data_out(wbr_ram_data_out), .wenable_in(wbr_wallow));
    `endif
`endif

/*-----------------------------------------------------------------------------------------------------------
Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
-----------------------------------------------------------------------------------------------------------*/
FIFO_CONTROL #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
              (.rclock_in(pci_clock_in), .wclock_in(wb_clock_in), .renable_in(wbw_renable_in), 
               .wenable_in(wbw_wenable_in), .reset_in(reset_in), .flush_in(wbw_flush_in), 
               .almost_full_out(wbw_almost_full_out), .full_out(wbw_full_out), 
               .almost_empty_out(wbw_almost_empty_out), .empty_out(wbw_empty), 
               .waddr_out(wbw_waddr), .raddr_out(wbw_raddr), 
               .rallow_out(wbw_rallow), .wallow_out(wbw_wallow)); 

FIFO_CONTROL #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
              (.rclock_in(wb_clock_in), .wclock_in(pci_clock_in), .renable_in(wbr_renable_in), 
               .wenable_in(wbr_wenable_in), .reset_in(reset_in), .flush_in(wbr_flush_in), 
               .almost_full_out(wbr_almost_full_out), .full_out(wbr_full_out), 
               .almost_empty_out(wbr_almost_empty_out), .empty_out(wbr_empty), 
               .waddr_out(wbr_waddr), .raddr_out(wbr_raddr), 
               .rallow_out(wbr_rallow), .wallow_out(wbr_wallow)); 


// in and out transaction counters
always@(posedge wb_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
        wbw_inTransactionCount <= #`FF_DELAY {WBW_ADDR_LENGTH{1'b0}} ;
    else
        if (wbw_last_in && wbw_wallow)
            wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
end

always@(posedge pci_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
        wbw_outTransactionCount <= #`FF_DELAY {WBW_ADDR_LENGTH{1'b0}} ;
    else
        if (wbw_last_out)
            wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
end

always@(posedge pci_clock_in or posedge wbr_clear)
begin
    if (wbr_clear)
        wbr_inTransactionCount <= #`FF_DELAY 1'b0 ;
    else
        if (wbr_last_in && wbr_wallow)
            wbr_inTransactionCount <= #`FF_DELAY ~wbr_inTransactionCount ;
end
        
always@(posedge wb_clock_in or posedge wbr_clear)
begin
    if (wbr_clear)
        wbr_outTransactionCount <= #`FF_DELAY 1'b0 ;
    else
        if (wbr_last_out)
            wbr_outTransactionCount <= #`FF_DELAY ~wbr_outTransactionCount ;
end

assign wbw_transaction_ready_out  = !(wbw_inTransactionCount == wbw_outTransactionCount)   ;
assign wbr_transaction_ready_out  = !(wbr_inTransactionCount == wbr_outTransactionCount) ;

endmodule