wbw_wbr_fifos.v

PCI IP核功能实现

wire wbw_wallow ;
wire wbw_rallow ;

/*-----------------------------------------------------------------------------------------------------------
wbr_wallow = WBR_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
wbr_rallow = WBR_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
-----------------------------------------------------------------------------------------------------------*/
wire wbr_wallow ;
wire wbr_rallow ;

/*-----------------------------------------------------------------------------------------------------------
wires for address port conections from WBW_FIFO control logic to RAM blocks used for WBW_FIFO
-----------------------------------------------------------------------------------------------------------*/
wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr ;
wire [(WBW_ADDR_LENGTH - 1):0] wbw_waddr ;

/*-----------------------------------------------------------------------------------------------------------
wires for address port conections from WBR_FIFO control logic to RAM blocks used for WBR_FIFO
-----------------------------------------------------------------------------------------------------------*/
wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr ;
wire [(WBR_ADDR_LENGTH - 1):0] wbr_waddr ;

/*-----------------------------------------------------------------------------------------------------------
WBW_FIFO transaction counters: used to count incoming transactions and outgoing transactions. When number of
input transactions is equal to number of output transactions, it means that there isn't any complete transaction
currently present in the FIFO.
-----------------------------------------------------------------------------------------------------------*/
reg [(WBW_ADDR_LENGTH - 1):0] wbw_inTransactionCount ;
reg [(WBW_ADDR_LENGTH - 1):0] wbw_outTransactionCount ;

/*-----------------------------------------------------------------------------------------------------------
FlipFlops for indicating if complete delayed read completion is present in the FIFO
-----------------------------------------------------------------------------------------------------------*/
reg wbr_inTransactionCount ;
reg wbr_outTransactionCount ;
/*-----------------------------------------------------------------------------------------------------------
wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
it means that there was one complete transaction taken out of FIFO.
-----------------------------------------------------------------------------------------------------------*/
wire wbw_last_in  = wbw_wallow && (wbw_control_in == `LAST) ;
wire wbw_last_out = wbw_rallow && (wbw_control_out == `LAST) ;

wire wbr_last_in  = wbr_wallow && (wbr_control_in == `LAST) ;
wire wbr_last_out = wbr_rallow && (wbr_control_out == `LAST) ;

wire wbw_empty ;
wire wbr_empty ;

assign wbw_empty_out = wbw_empty ;
assign wbr_empty_out = wbr_empty ;

// clear wires for fifos
wire wbw_clear = reset_in || wbw_flush_in ; // WBW_FIFO clear
wire wbr_clear = reset_in || wbr_flush_in ; // WBR_FIFO clear

`ifdef FPGA
/*-----------------------------------------------------------------------------------------------------------
this code is included only for FPGA core usage - somewhat different logic because of sharing
one block selectRAM+ between two FIFOs
-----------------------------------------------------------------------------------------------------------*/
    `ifdef BIG
        /*-----------------------------------------------------------------------------------------------------------
        Big FPGAs
        WBW_FIFO and WBR_FIFO address prefixes - used for extending read and write addresses because of varible
        FIFO depth and fixed SelectRAM+ size. Addresses are zero paded on the left to form long enough address
        -----------------------------------------------------------------------------------------------------------*/
        wire [(7 - WBW_ADDR_LENGTH):0] wbw_addr_prefix = {( 8 - WBW_ADDR_LENGTH){1'b0}} ;
        wire [(7 - WBR_ADDR_LENGTH):0] wbr_addr_prefix = {( 8 - WBR_ADDR_LENGTH){1'b0}} ;

        // compose addresses
        wire [7:0] wbw_whole_waddr = {wbw_addr_prefix, wbw_waddr} ;
        wire [7:0] wbw_whole_raddr = {wbw_addr_prefix, wbw_raddr} ;
        
        wire [7:0] wbr_whole_waddr = {wbr_addr_prefix, wbr_waddr} ;
        wire [7:0] wbr_whole_raddr = {wbr_addr_prefix, wbr_raddr} ;

        /*-----------------------------------------------------------------------------------------------------------
        Only 8 bits out of 16 are used in ram3 and ram6 - wires for referencing them
        -----------------------------------------------------------------------------------------------------------*/
        wire [15:0] dpram3_portB_output ;
        wire [15:0] dpram6_portA_output ;

        /*-----------------------------------------------------------------------------------------------------------
        Control out assignements from ram3 output
        -----------------------------------------------------------------------------------------------------------*/
        assign wbw_control_out = dpram3_portB_output[15:12] ;
        assign wbr_control_out = dpram6_portA_output[15:12] ;

        assign wbw_cbe_out = dpram3_portB_output[3:0] ;
        assign wbr_be_out  = dpram6_portA_output[3:0] ;

        wire wbw_read_enable = wbw_rallow || wbw_empty ;
        wire wbr_read_enable = wbr_rallow || wbr_empty ;
        
        // Block SelectRAM+ cells instantiation
        RAMB4_S16_S16 dpram16_1 (.ADDRA(wbw_whole_waddr), .DIA(wbw_addr_data_in[15:0]), 
                                 .ENA(vcc), .RSTA(reset_in),
                                 .CLKA(wb_clock_in), .WEA(wbw_wallow), 
                                 .DOA(),
                                 .ADDRB(wbw_whole_raddr), .DIB(16'h0000), 
                                 .ENB(wbw_read_enable), .RSTB(reset_in),
                                 .CLKB(pci_clock_in), .WEB(gnd), 
                                 .DOB(wbw_addr_data_out[15:0])) ;

        RAMB4_S16_S16 dpram16_2 (.ADDRA(wbw_whole_waddr), .DIA(wbw_addr_data_in[31:16]), 
                                 .ENA(vcc), .RSTA(reset_in),
                                 .CLKA(wb_clock_in), .WEA(wbw_wallow), 
                                 .DOA(),
                                 .ADDRB(wbw_whole_raddr), .DIB(16'h0000), 
                                 .ENB(wbw_read_enable), .RSTB(reset_in),
                                 .CLKB(pci_clock_in), .WEB(gnd), 
                                 .DOB(wbw_addr_data_out[31:16])) ;
    
        RAMB4_S16_S16 dpram16_3 (.ADDRA(wbw_whole_waddr), .DIA({wbw_control_in, 8'h00, wbw_cbe_in}), 
                                 .ENA(vcc), .RSTA(reset_in),
                                 .CLKA(wb_clock_in), .WEA(wbw_wallow), 
                                 .DOA(),
                                 .ADDRB(wbw_whole_raddr), .DIB(16'h0000), 
                                 .ENB(wbw_read_enable), .RSTB(reset_in),
                                 .CLKB(pci_clock_in), .WEB(gnd), 
                                 .DOB(dpram3_portB_output)) ;

        RAMB4_S16_S16 dpram16_4 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000), 
                                 .ENA(wbr_read_enable), .RSTA(reset_in),
                                 .CLKA(wb_clock_in), .WEA(gnd), 
                                 .DOA(wbr_data_out[15:0]),
                                 .ADDRB(wbr_whole_waddr), .DIB(wbr_data_in[15:0]), 
                                 .ENB(vcc), .RSTB(reset_in),
                                 .CLKB(pci_clock_in), .WEB(wbr_wallow), 
                                 .DOB()) ;

        RAMB4_S16_S16 dpram16_5 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000), 
                                 .ENA(wbr_read_enable), .RSTA(reset_in),
                                 .CLKA(wb_clock_in), .WEA(gnd), 
                                 .DOA(wbr_data_out[31:16]),
                                 .ADDRB(wbr_whole_waddr), .DIB(wbr_data_in[31:16]), 
                                 .ENB(vcc), .RSTB(reset_in),
                                 .CLKB(pci_clock_in), .WEB(wbr_wallow), 
                                 .DOB()) ;
    
        RAMB4_S16_S16 dpram16_6 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000), 
                                 .ENA(wbr_read_enable), .RSTA(reset_in),
                                 .CLKA(wb_clock_in), .WEA(gnd), 
                                 .DOA(dpram6_portA_output),
                                 .ADDRB(wbr_whole_waddr), .DIB({wbr_control_in, 8'h00, wbr_be_in}), 
                                 .ENB(vcc), .RSTB(reset_in),
                                 .CLKB(pci_clock_in), .WEB(wbr_wallow), 
                                 .DOB()) ;

    `else // SMALL FPGAs

        /*-----------------------------------------------------------------------------------------------------------
        Small FPGAs
        WBW_FIFO and WBR_FIFO address prefixes - used for extending read and write addresses because of varible
        FIFO depth and fixed SelectRAM+ size. Addresses are always paded, because of RAM sharing between FIFOs
        WBW addresses are zero padded on the left, WBR addresses are padded
        with ones on the left
        -----------------------------------------------------------------------------------------------------------*/
        wire [(7 - WBW_ADDR_LENGTH):0] wbw_addr_prefix = {( 8 - WBW_ADDR_LENGTH){1'b0}} ;
        wire [(7 - WBR_ADDR_LENGTH):0] wbr_addr_prefix = {( 8 - WBR_ADDR_LENGTH){1'b1}} ;

        /*-----------------------------------------------------------------------------------------------------------
        Only 8 bits out of 16 are used in ram3 - wires for referencing them
        -----------------------------------------------------------------------------------------------------------*/
        wire [15:0] dpram3_portA_output ;
        wire [15:0] dpram3_portB_output ;

        /*-----------------------------------------------------------------------------------------------------------
        Control out assignements from ram3 output
        -----------------------------------------------------------------------------------------------------------*/
        assign wbw_control_out = dpram3_portB_output[15:12] ;
        assign wbr_control_out = dpram3_portA_output[15:12] ;

        assign wbw_cbe_out = dpram3_portB_output[3:0] ;
        assign wbr_be_out  = dpram3_portA_output[3:0] ;
        
        /*-----------------------------------------------------------------------------------------------------------
        Logic used for extending port's enable input for one clock cycle to allow address and date change from 
        WISHBONE write fifo's write address and data back to WISHBONE read fifo's address and data ( turnaround cycle )
        -----------------------------------------------------------------------------------------------------------*/
        reg wbw_write_performed ;
        always@(posedge wb_clock_in or posedge reset_in)
        begin
            if (reset_in)
                wbw_write_performed <= #`FF_DELAY 1'b0 ;
            else 
                wbw_write_performed <= #`FF_DELAY wbw_wallow ;
        end

        /*-----------------------------------------------------------------------------------------------------------
        Logic used for extending port's enable input for one clock cycle to allow address and date change from 
        WISHBONE read fifo's write address and data back to WISHBONE write fifo's address and data ( turnaround cycle )
        -----------------------------------------------------------------------------------------------------------*/
        reg wbr_write_performed ;
        always@(posedge pci_clock_in or posedge reset_in)
        begin
            if (reset_in)