wb_slave.v

PCI IP核功能实现

                    begin //~rattempt
                        n_state <= S_READ ; // stay in this state
                            
                        // response signals inactive
                        ack         <= 1'b0 ;
                        rty         <= 1'b0 ;
                        err         <= 1'b0 ;

                        // read controls - inactive - master inserting WS
                        wbr_fifo_flush   <= 1'b0 ;
                        wbr_fifo_renable <= 1'b0 ;
                        del_req          <= 1'b0 ;
                        del_done         <= 1'b0 ;
                    end //~rattempt
                end //burst_transfer
                else //~burst_transfer
                begin
                    // this isn't a burst transfer - return to IDLE state
                    n_state <= S_IDLE ;
                    
                    // do not respond with any signal
                    ack         <= 1'b0 ;
                    rty         <= 1'b0 ;
                    err         <= 1'b0 ;

                    // read signals : signal that read completion has finished on WISHBONE and flush FIFO
                    wbr_fifo_flush   <= 1'b1 ;
                    wbr_fifo_renable <= 1'b0 ;
                    del_req          <= 1'b0 ;
                    del_done         <= 1'b1 ;
                    
                end //~burst_transfer
            end // S_READ

    S_TURN_ARROUND:begin
                        // turn-arround is provided for FIFO - it does everything necesarry by itself
                        n_state <= S_IDLE ; // next state is always idle

                        // response signals inactive
                        ack         <= 1'b0 ;
                        rty         <= 1'b0 ;
                        err         <= 1'b0 ;

                        //write signals inactive
                        wbw_fifo_control <= `ADDRESS ;
                        wbw_fifo_wenable <= 1'b0 ;            
                        d_incoming_ena   <= 1'b0 ;
                        
                        // read signals inactive
                        wbr_fifo_flush   <= 1'b0 ;
                        wbr_fifo_renable <= 1'b0 ;
                        del_req          <= 1'b0 ;
                        del_done         <= 1'b0 ;

                        // configuration space control signals inactive
                        conf_wenable <= 1'b0 ;
                        conf_renable <= 1'b0 ;

						// WISHBONE data output selection - drive wbr_output
	                    sdata_o_sel <= WBR_SEL ;

                        // read is not in progress
                        del_in_progress_out <= 1'b0 ;
	                    
                    end // S_TURN_ARROUND
    S_CONF_WRITE:  begin
                        n_state <= S_IDLE ; // next state after configuration access is always idle

                        //image write signals inactive
                        wbw_fifo_control <= `ADDRESS ;
                        wbw_fifo_wenable <= 1'b0 ;            
                        d_incoming_ena   <= 1'b0 ;
                        
                        // image read signals inactive
                        wbr_fifo_flush   <= 1'b0 ;
                        wbr_fifo_renable <= 1'b0 ;
                        
                        // configuration space read enable control signal inactive
                        conf_renable <= 1'b0 ;

						// WISHBONE data output selection - drive wbr_output
	                    sdata_o_sel <= WBR_SEL ;

                        if (wb_conf_hit_in && wattempt)
                        begin
                            if (burst_transfer || // bursts not allowed to configuration space
                                sel_error )       // illegal address and select lines combination
                            begin
                                // burst transfer to configuration space
                                // respond with an error
                                ack         <= 1'b0 ;
                                rty         <= 1'b0 ;
                                err         <= 1'b1 ;

                                // configuration access write enable control signal inactive
                                conf_wenable <= 1'b0 ;
                                
                                // delayed request signals inactive
                                del_req  <= 1'b0 ;
                                del_done <= 1'b0 ;

                                // delayed is not in progress since this is an error
                                del_in_progress_out <= 1'b0 ;

                            end //error
                            else
                        
                        `ifdef GUEST
                            begin
                                // guest bridge doesn't have write access to configuration space
                                conf_wenable <= 1'b0 ;
                            
                                // acknowledge the cycle
                                rty <= 1'b0 ;
                                ack <= 1'b1 ;
                                err <= 1'b0 ;
                                
                                // delayed request signals inactive
                                del_req  <= 1'b0 ;
                                del_done <= 1'b0 ;

                                // delayed transaction is not in progress
                                del_in_progress_out <= 1'b0 ;
                             end
                    
                        `else
                        `ifdef HOST
                            // check whether this is a write to conf. cycle register
                            if ( ccyc_hit ) 
                            begin
                                conf_wenable <= 1'b0 ; 
                                // retry
                                if (~do_ccyc_req && ~do_ccyc_comp) // neither request or completion can be performed at this time - retry
                                begin

                                    rty <= 1'b1 ;
                                    ack <= 1'b0 ;
                                    err <= 1'b0 ;
    
                                    // delayed request signals inactive
                                    del_req  <= 1'b0 ;
                                    del_done <= 1'b0 ;
                            
                                    // delayed transaction is not in progress
                                    del_in_progress_out <= 1'b0 ;

                                end //retry
                                else
                                if (do_ccyc_req)
                                begin
                                    // request can be issued - respond with retry
                                    rty <= 1'b1 ;
                                    ack <= 1'b0 ;
                                    err <= 1'b0 ;
    
                                    // issue delayed request
                                    del_req  <= 1'b1 ;
                                    del_done <= 1'b0 ;

                                    // delayed completion is not in progress
                                    del_in_progress_out <= 1'b0 ;
                                end
                                else // do ccyc completion
                                begin 
                                    
                                    // signal completion done and in progress
                                    del_req  <= 1'b0 ;
                                    del_done <= 1'b1 ;
                                    del_in_progress_out <= 1'b1 ;
                                    
                                    if (del_error_in) // request was finished with target abort - signal an error
                                    begin
                                        rty <= 1'b0 ;
                                        ack <= 1'b0 ;
                                        err <= 1'b1 ;
                                    
                                    end // del_error_in
                                    else
                                    begin // ccyc master abort or normal
                                        rty <= 1'b0 ;
                                        ack <= 1'b1 ;
                                        err <= 1'b0 ;
                                    end
                                end //ccyc completion
                            end //conf_cyc_hit
                            else //ordinary configuration hit                    
                            begin
    
                                // enable configuration space write
                                conf_wenable <= 1'b1 ;
    
                                // acknowledge the cycle
                                rty <= 1'b0 ;
                                ack <= 1'b1 ;
                                err <= 1'b0 ;
                                
                                // delayed request controls inactive
                                del_req  <= 1'b0 ;
                                del_done <= 1'b0 ;
                                del_in_progress_out <= 1'b0 ;
    
                            end //ordinary configuration hit
                        `endif
                        `endif
                        end // wb_conf_hit_in
                      
                        else // no conf hit
                        begin
                            rty <= 1'b0 ;
                            ack <= 1'b0 ;
                            err <= 1'b0 ;

                            // configuration write enable inactive
                            conf_wenable <= 1'b0 ;

                            // configuration cycle controls inactive
                            del_req  <= 1'b0 ;
                            del_done <= 1'b0 ;
                            del_in_progress_out <= 1'b0 ;

                        end // no conf hit
                    
                    end // S_CONF_WRITE

    S_CONF_READ:   begin
                        n_state <= S_IDLE ; // next state after configuration access is always idle

                        //image write signals inactive
                        wbw_fifo_control <= `ADDRESS ;
                        wbw_fifo_wenable <= 1'b0 ;            
                        d_incoming_ena   <= 1'b0 ;
                        
                        // image read signals inactive
                        wbr_fifo_flush   <= 1'b0 ;
                        
                        // configuration space write enable control signal inactive
                        conf_wenable <= 1'b0 ;
                        
                        if(wb_conf_hit_in && rattempt) // read from configuration space
                        begin 
    
                            if (burst_transfer || // bursts not allowed to configuration space
                                sel_error )       // illegal address and select lines combination
                            begin
                                // respond with an error
                                ack         <= 1'b0 ;
                                rty         <= 1'b0 ;
                                err         <= 1'b1 ;
                                
                                // delayed request control inactive
                                del_req  <= 1'b0 ;
                                del_done <= 1'b0 ;                        
                                
                                // delayed transaction is not in progress
                                del_in_progress_out <= 1'b0 ;

                                // configuration read enable inactive
                                conf_renable <= 1'b0 ;
    
    							// WISHBONE data output selection - drive configuration output
			                    sdata_o_sel <= CONF_SEL ;

                                // fifo read enable inactive
                                wbr_fifo_renable <= 1'b0 ;
			                    
                            end //error
                            else
                            
                        `ifdef GUEST
                            
                            begin // ordinary configuration read
                                ack         <= 1'b1 ;