wb_slave.v

PCI IP核功能实现

                                // read is in progress
                                del_in_progress_out <= 1'b1 ;

                            end // no DATA_ERROR

                        end // do_dread_completion
                    end //wb_hit_in
                    else //~wb_hit
                    if(wb_conf_hit_in) // read from configuration space
                    begin 
                        n_state <= S_CONF_READ ; // go to configuration space read state - give outputs one clock cycle for setup

                        // image read signals inactive
                        wbr_fifo_flush   <= 1'b0 ;
                        wbr_fifo_renable <= 1'b0 ;
                        del_req      <= 1'b0 ;
                        del_done     <= 1'b0 ;

                        // do not respond yet
                        ack         <= 1'b0 ;
                        rty         <= 1'b0 ;
                        err         <= 1'b0 ;

						// WISHBONE data output selection - drive configuration space output
	                    sdata_o_sel <= CONF_SEL ;

                        // read is not in progress since this is configuration read
                        del_in_progress_out <= 1'b0 ;
	                    
                    end //read from configuration space

                    else // no hit

                    begin
                        n_state <= S_IDLE ; 
                        wbr_fifo_flush   <= 1'b0 ;
                        wbr_fifo_renable <= 1'b0 ;
                        del_req      <= 1'b0 ;
                        del_done     <= 1'b0 ;
                        ack         <= 1'b0 ;
                        rty         <= 1'b0 ;
                        err         <= 1'b0 ;

                        // WISHBONE data output selection - drive wbr_output
	                    sdata_o_sel <= WBR_SEL ;
	                    
                        // read is not in progress since there is no image hit
                        del_in_progress_out <= 1'b0 ;

                    end // no hit
                end //if (rattempt)
                else // no write and no read attempt - do nothing
                begin
                    n_state <= S_IDLE ; 
    
                    // write signals - all in inactive state
                    wbw_fifo_control <= `ADDRESS ;
                    wbw_fifo_wenable <= 1'b0 ;            
                    d_incoming_ena   <= 1'b0 ;
            
                    // handshaking signals inactive
                    ack         <= 1'b0 ;
                    rty         <= 1'b0 ;
                    err         <= 1'b0 ;

                    //  read signals inactive
                    wbr_fifo_flush   <= 1'b0 ;
                    wbr_fifo_renable <= 1'b0 ;
                    del_req          <= 1'b0 ;
                    del_done         <= 1'b0 ;

                    // configuration space control signals inactive
                    conf_wenable <= 1'b0 ;
                    conf_renable <= 1'b0 ;

                    // WISHBONE data output selection - drive wbr_output
	                sdata_o_sel <= WBR_SEL ;

                    // read is not in progress
                    del_in_progress_out <= 1'b0 ;
	                    
                end //no write and no read attempt                
            end //`S_IDLE
    S_W_ADDR_DATA: begin
                        // read signals inactive
                        wbr_fifo_flush   <= 1'b0 ;
                        wbr_fifo_renable <= 1'b0 ;
                        del_req          <= 1'b0 ;
                        del_done         <= 1'b0 ;

                        // configuration space control signals inactive
                        conf_wenable <= 1'b0 ;
                        conf_renable <= 1'b0 ;

                       	// WISHBONE data output selection - drive wbr_output
	                    sdata_o_sel <= WBR_SEL ;

                        // delayed transaction is not in progress when receiving posted burst write	                    
                        del_in_progress_out <= 1'b0 ;

                        if (burst_transfer)
                            if (wattempt)
                            begin
                                // check for error conditions
                                if ( ~same_hit ||             // burst transfer crossed image range
                                     ~alligned_address )    // address is not alligned
                                begin
                                    n_state <= S_TURN_ARROUND ; // goto turn-arround state
                                    
                                    // respond with an error
                                    ack         <= 1'b0 ;
                                    rty         <= 1'b0 ;
                                    err         <= 1'b1 ;
    
                                    // write data latched in itermediate register and tag it as last
                                    wbw_fifo_control <= `LAST ;
                                    wbw_fifo_wenable <= 1'b1 ;            
                                    d_incoming_ena   <= 1'b0 ;

                                end // error
                                else //no error
                                // check for retry condition
                                if (~img_wallow)
                                begin
                                    n_state <= S_TURN_ARROUND ; // FIFO was filled or error lock occurred - goto turnarround state

                                    // respond with retry
                                    ack         <= 1'b0 ;
                                    rty         <= 1'b1 ;
                                    err         <= 1'b0 ;

                                    // write last data latched in intermediate register
                                    wbw_fifo_control <= `LAST ;
                                    wbw_fifo_wenable <= 1'b1 ;            
                                    d_incoming_ena   <= 1'b0 ;
                                    
                                end // retry    
                                else // no error and no retry - acknowledge
                                begin
                                    n_state <= S_W_ADDR_DATA ; // stay in current state
                                    
                                    // respond with acknowledge
                                    ack         <= 1'b1 ;
                                    rty         <= 1'b0 ;
                                    err         <= 1'b0 ;
                    
                                    // write data from intermediate register to fifo and latch new data provided
                                    wbw_fifo_control <= `DATA ;
                                    wbw_fifo_wenable <= 1'b1 ;            
                                    d_incoming_ena   <= 1'b1 ;
                                    
                                end // no error and no retry - acknowledge
                            end // wattempt
                            else // no write attempt
                            begin
                                n_state <= S_W_ADDR_DATA ; // master is inserting WS - stay in current state

                                // response signals inactive
                                ack         <= 1'b0 ;
                                rty         <= 1'b0 ;
                                err         <= 1'b0 ;

                                //write signals inactive
                                wbw_fifo_control <= `DATA ;
                                wbw_fifo_wenable <= 1'b0 ;            
                                d_incoming_ena   <= 1'b0 ;
                                
                            end // no write attempt
                        else // ~burst transfer
                        begin
                            n_state <= S_TURN_ARROUND ; // no burst transfer - go back to idle
                            
                            // do not respond
                            ack         <= 1'b0 ;
                            rty         <= 1'b0 ;
                            err         <= 1'b0 ;
                            
                            // write last data to FIFO and don't latch new data
                            wbw_fifo_control <= `LAST ;
                            wbw_fifo_wenable <= 1'b1 ;            
                            d_incoming_ena   <= 1'b0 ;
                            
                        end // burst_transfer
                    end // S_W_ADDR_DATA

    S_READ:begin
                // write signals in inactive state
                wbw_fifo_control <= `ADDRESS ;
                wbw_fifo_wenable <= 1'b0 ;            
                d_incoming_ena   <= 1'b0 ;
                
                // configuration space control signals inactive
                conf_wenable <= 1'b0 ;
                conf_renable <= 1'b0 ;

				// WISHBONE data output selection - drive wbr_output
	            sdata_o_sel <= WBR_SEL ;
	            
                // this state is for reads only - in this state read is in progress all the time
                del_in_progress_out <= 1'b1 ;

                if(burst_transfer)
                begin
                    if(rattempt)
                    begin
                        // check for error conditions
                        if (~same_hit || // read passed image's range
                            ~alligned_address ) // address is not alligned within burst transfer
                        begin
                            // return to idle state
                            n_state <= S_IDLE ;
                    
                            // signal an error
                            ack         <= 1'b0 ;
                            rty         <= 1'b0 ;
                            err         <= 1'b1 ;

                            // read signals : signal that read completion has finished on WISHBONE and flush FIFO
                            wbr_fifo_flush   <= 1'b1 ;
                            wbr_fifo_renable <= 1'b0 ;
                            del_req          <= 1'b0 ;
                            del_done         <= 1'b1 ;
                        end // error
                        else
                        if (wbr_fifo_control_in == `DATA_ERROR)
                        begin
                            // signal an error has occured on PCI bus during this location read
                            n_state <= S_IDLE ; // go back to idle state
                            
                            // respond with error
                            ack         <= 1'b0 ;
                            rty         <= 1'b0 ;
                            err         <= 1'b1 ;

                            // read controls - enable fifo read and signal that read is finished
                            wbr_fifo_flush   <= 1'b0 ;
                            wbr_fifo_renable <= 1'b1 ;
                            del_req          <= 1'b0 ;
                            del_done         <= 1'b1 ;
                        end
                        else
                        if (wbr_fifo_almost_empty_in) // WB is now reading last data from FIFO
                        begin
                            n_state <= S_IDLE ; // go back to idle state
                            
                            // acknowledge the transaction
                            ack         <= 1'b1 ;
                            rty         <= 1'b0 ;
                            err         <= 1'b0 ;

                            // read controls - enable fifo read and signal that read is finished
                            wbr_fifo_flush   <= 1'b0 ;
                            wbr_fifo_renable <= 1'b1 ;
                            del_req          <= 1'b0 ;
                            del_done         <= 1'b1 ;

                        end //wbr_fifo_almost_empty_in
                        else //~wbr_fifo_almost_empty_in
                        begin
                            n_state <= S_READ ; // stay in this state
                            
                            // acknowledge the transaction
                            ack         <= 1'b1 ;
                            rty         <= 1'b0 ;
                            err         <= 1'b0 ;

                            // read controls - enable fifo read
                            wbr_fifo_flush   <= 1'b0 ;
                            wbr_fifo_renable <= 1'b1 ;
                            del_req          <= 1'b0 ;
                            del_done         <= 1'b0 ;
                        end //~wbr_fifo_almost_empty_in
                    end //rattempt
                    else