wb_slave.v

PCI IP核功能实现

        wb_conf_hit_in              or
        sel_error                   or
        do_ccyc_req                 or 
        do_ccyc_comp                or
        ccyc_hit                    or
        del_write_in                or
        del_error_in                or
        do_iack_req                 or
        do_iack_comp                or
        iack_hit                    or
        hit_error
       )
begin    
    case (c_state)
    S_IDLE:begin
                if (wattempt)
                begin
                    // read signals in inactive state when writes are in progress
                    wbr_fifo_flush   <= 1'b0 ;
                    wbr_fifo_renable <= 1'b0 ;
                    
                    // configuration read enable control signal inactive
                    conf_renable <= 1'b0 ;
                        
                    // WISHBONE data output selection - since this is a write, hold wbr output
                    sdata_o_sel <= WBR_SEL ;

                    // read cannot be in progress while write is attempted
                    del_in_progress_out <= 1'b0 ;

                    // delayed request signals inactive
                    del_req  <= 1'b0 ;
                    del_done <= 1'b0 ;
        
                    // configuration access control signals inactive
                    conf_wenable <= 1'b0 ;
                    conf_renable <= 1'b0 ;

                    if(wb_hit_in)
                    begin

                        // check error conditions for image writes
                        if ( 
                            (map && (burst_transfer || sel_error)) || // IO write is a burst or has wrong select lines active= Error
                            (~map && ~alligned_address) ||  // Mem write to nonaligned address = error
                            hit_error                       // images overlaping - error
                           )
                        begin
                            n_state <= S_IDLE ; // stay in idle state because of an error condition

                            // respond with an error
                            ack         <= 1'b0 ;
                            rty         <= 1'b0 ;
                            err         <= 1'b1 ;

                            // write signals in inactive state
                            wbw_fifo_control <= `ADDRESS ;
                            wbw_fifo_wenable <= 1'b0 ;            
                            d_incoming_ena   <= 1'b0 ;
           
                        end // error conditions
                        else
                        // check for retry conditions for image writes
                        if ( ~img_wallow ) // write to image not allowed at this time = retry
                        begin
                            n_state <= S_IDLE ; // stay in IDLE
                            
                            // respond with a retry
                            ack         <= 1'b0 ;
                            rty         <= 1'b1 ;
                            err         <= 1'b0 ;

                            // write signals in inactive state
                            wbw_fifo_control <= `ADDRESS ;
                            wbw_fifo_wenable <= 1'b0 ;            
                            d_incoming_ena   <= 1'b0 ;
                            
                        end //retry
                        else // everything OK - proceed
                        begin
                            n_state <= S_W_ADDR_DATA ; // goto write transfer state
            
                            // respond with acknowledge
                            ack         <= 1'b1 ;
                            rty         <= 1'b0 ;
                            err         <= 1'b0 ;

                            // write control signals
                            // fifo is enabled - address is written to it with appropriate control encoding
                            wbw_fifo_control <= `ADDRESS ;
                            wbw_fifo_wenable <= 1'b1 ;            
                            // data is latched to data incoming intermidiate stage - it will be put in FIFO later
                            d_incoming_ena   <= 1'b1 ;
                            
                        end // image write OK
                    end //wb_hit_in
                    else // no image hit

                    if (wb_conf_hit_in) // configuration space hit
                    begin
                        // image write control signals inactive - give outputs one clock cycle setup time
                        n_state <= S_CONF_WRITE ; // go to conf. write state
                            
                        // don't respond yet
                        ack         <= 1'b0 ;
                        rty         <= 1'b0 ;
                        err         <= 1'b0 ;

                        // write signals in inactive state
                        wbw_fifo_control <= `ADDRESS ;
                        wbw_fifo_wenable <= 1'b0 ;            
                        d_incoming_ena   <= 1'b0 ;

                    end // wb_conf_hit_in*/
                    else
                    begin // no hit
                        n_state <= S_IDLE ; // stay in IDLE
                            
                        // don't respond
                        ack         <= 1'b0 ;
                        rty         <= 1'b0 ;
                        err         <= 1'b0 ;

                        // write signals in inactive state
                        wbw_fifo_control <= `ADDRESS ;
                        wbw_fifo_wenable <= 1'b0 ;            
                        d_incoming_ena   <= 1'b0 ;

                    end // no hit                        
                end //wattempt
                else
                if (rattempt)
                begin
                    // write signals in inactive state
                    wbw_fifo_control <= `ADDRESS ;
                    wbw_fifo_wenable <= 1'b0 ;            
                    d_incoming_ena   <= 1'b0 ;

                    // configuration access signals inactive
                    conf_wenable <= 1'b0 ;
                    conf_renable <= 1'b0 ;
						
                    if(wb_hit_in)
                    begin
						// WISHBONE data output selection - drive wbr_output
	                    sdata_o_sel <= WBR_SEL ;
	                    
                        // check error conditions for image reads
                        if ( 
                            (map && (burst_transfer || sel_error)) || // IO read is a burst or has wrong select lines active= Error
                            (~map && ~alligned_address) || // Mem read from nonaligned address = error
                            hit_error                      // images overlaping - error
                           )
                        begin
                            n_state <= S_IDLE ; // stay in idle because of an error
                            
                            // respond with error
                            ack         <= 1'b0 ;
                            rty         <= 1'b0 ;
                            err         <= 1'b1 ;
    
                            // read controls inactive
                            wbr_fifo_flush   <= 1'b0 ;
                            wbr_fifo_renable <= 1'b0 ;
                            del_req      <= 1'b0 ;
                            del_done     <= 1'b0 ;

                            // read is not in progress
                            del_in_progress_out <= 1'b0 ;
                            
                        end // error conditions
                        else
                        
                        // check for retry conditions for image reads
                        if ( ~do_dread_request && ~do_dread_completion) // read through image not allowed at this time = retry
                        begin
                            n_state <= S_IDLE ; // stay in idle state
                            
                            // respond with retry
                            ack         <= 1'b0 ;
                            rty         <= 1'b1 ;
                            err         <= 1'b0 ;
    
                            // read controls inactive
                            wbr_fifo_flush   <= 1'b0 ;
                            wbr_fifo_renable <= 1'b0 ;
                            del_req      <= 1'b0 ;
                            del_done     <= 1'b0 ;

                            // read is not in progress
                            del_in_progress_out <= 1'b0 ;
                        
                        end //retry
                        else
                        if ( do_dread_request ) // read request can be accepted
                        begin
                            n_state <= S_IDLE ; // stay in IDLE

                            // respond with retry
                            ack         <= 1'b0 ; 
                            rty         <= 1'b1 ;
                            err         <= 1'b0 ;

                            // FIFO signals inactive
                            wbr_fifo_flush   <= 1'b0 ;
                            wbr_fifo_renable <= 1'b0 ;
                    
                            // signal read request
                            del_req      <= 1'b1 ;
                            del_done     <= 1'b0 ;

                            // read is not in progress
                            del_in_progress_out <= 1'b0 ;
                            
                        end //do_dread_request
                        else // do_dread_completion
                        begin
                            // check if data is error message
                            if (wbr_fifo_control_in == `DATA_ERROR)
                            begin
                                n_state <= S_IDLE ; // stay in idle state
                            
                                // respond with error
                                ack         <= 1'b0 ;
                                rty         <= 1'b0 ;
                                err         <= 1'b1 ;

                                // read from FIFO to free up location that error is taking up
                                wbr_fifo_flush   <= 1'b0 ;
                                wbr_fifo_renable <= 1'b1 ;

                                // respond that read is finished
                                del_req      <= 1'b0 ;
                                del_done     <= 1'b1 ;

                                // read is in progress nevertheless it was terminated with an error
                                del_in_progress_out <= 1'b1 ;

                            end // DATA_ERROR
                            else
                            if (wbr_fifo_almost_empty_in)
                            begin
                                // only one location is in the FIFO - acknowledge the transfer and stay in this state
                                n_state <= S_IDLE ; // stay in idle state
                            
                                // respond with acknowledge
                                ack         <= 1'b1 ;
                                rty         <= 1'b0 ;
                                err         <= 1'b0 ;

                                // read from FIFO
                                wbr_fifo_flush   <= 1'b0 ;
                                wbr_fifo_renable <= 1'b1 ;

                                // respond that read is finished
                                del_req      <= 1'b0 ;
                                del_done     <= 1'b1 ;

                                // read is in progress
                                del_in_progress_out <= 1'b1 ;
                            end
                            else
                            begin
                                n_state <= S_READ ; // go to read state
                            
                                // respond with acknowledge since data output from FIFO is always prepared
                                ack         <= 1'b1 ;
                                rty         <= 1'b0 ;
                                err         <= 1'b0 ;

                                //  enable read from FIFO - on posedge of clock new data will be provided
                                wbr_fifo_flush   <= 1'b0 ;
                                wbr_fifo_renable <= 1'b1 ;
                                del_req      <= 1'b0 ;
                                del_done     <= 1'b0 ;