wb_slave.v

PCI IP核功能实现

reg d_incoming_ena ;

// incoming data register control logic
always@(posedge wb_clock_in or posedge reset_in)
begin
	if (reset_in)
		d_incoming <= #`FF_DELAY {35{1'b0}} ;
	else if (d_incoming_ena)
		d_incoming <= #`FF_DELAY {SEL_I, SDATA_I} ;
end

/*===================================================================================================================================================================================
Write allow for image accesses. Writes through images are allowed when all of following are true:
- WBW_FIFO musn't be almost full nor full for image writes to be allowed - Every transaction takes at least two locations in the FIFO
- delayed read from from WISHBONE to PCI request musn't be present
- delayed read from PCI to WISHBONE completion musn't be present
- lock input musn't be set - it can be set because of error reporting or because PCI master state machine is disabled
===================================================================================================================================================================================*/
wire img_wallow           = ~|{ wbw_fifo_almost_full_in , wbw_fifo_full_in, (wb_del_req_pending_in && ~del_write_in) , pci_drcomp_pending_in, wbs_lock_in } ;

/*===================================================================================================================================================================================
WISHBONE slave can request an image read accesses when all of following are true:
- delayed completion is not present
- delayed request is not present
- operation is not locked because of error reporting mechanism or because PCI master is disabled
===================================================================================================================================================================================*/
wire do_dread_request     = ~|{ wb_del_req_pending_in, wb_del_comp_pending_in, wbs_lock_in } ;

/*===================================================================================================================================================================================
WISHBONE slave can complete an image read accesses when all of following are true:
- delayed read completion is present
- delayed read completion is the same as current read access ( dread_completion_hit is 1 )
- PCI Write FIFO is empty - no posted write is waiting to be finished in PCIW_FIFO
- WBR_FIFO empty status is active
===================================================================================================================================================================================*/
wire select_and_bc_hit = ( SEL_I == wb_del_be_in ) && ( del_bc == del_bc_in ) ;
wire dread_completion_hit = ( wb_del_addr_in == wb_addr_in ) && select_and_bc_hit && ~del_write_in ;
wire do_dread_completion  = wb_del_comp_pending_in && pciw_fifo_empty_in && dread_completion_hit && ~wbr_fifo_empty_in ;

`ifdef GUEST

    // wires indicating allowance for configuration cycle generation requests
    wire do_ccyc_req  = 1'b0 ;
    wire do_ccyc_comp = 1'b0 ;
    
    // wires indicating allowance for interrupt acknowledge cycle generation requests
    wire do_iack_req  = 1'b0 ;
    wire do_iack_comp = 1'b0 ;

    // variables for configuration access control signals
    reg conf_wenable ;
    assign wb_conf_wenable_out = 1'b0 ;

    // configuration cycle data register hit
    wire ccyc_hit = 1'b0 ;
    wire iack_hit = 1'b0 ;

`else
`ifdef HOST
    // only host implementation has access for generating interrupt acknowledge and configuration cycles

    // wires indicating allowance for configuration cycle generation requests
    wire do_ccyc_req  = ~|{ wb_del_comp_pending_in, wb_del_req_pending_in, wbs_lock_in } ;
    wire do_ccyc_comp = wb_del_comp_pending_in && select_and_bc_hit && ((pciw_fifo_empty_in && ~del_write_in && ~wbr_fifo_empty_in) || del_write_in) ;
    
    // wires indicating allowance for interrupt acknowledge cycle generation requests
    wire do_iack_req  = ~|{ wb_del_comp_pending_in, wb_del_req_pending_in, wbs_lock_in } ;
    wire do_iack_comp = wb_del_comp_pending_in && select_and_bc_hit && pciw_fifo_empty_in && ~del_write_in && ~wbr_fifo_empty_in;

    // variables for configuration access control signals
    reg conf_wenable ;
    assign wb_conf_wenable_out = conf_wenable ;

    // configuration cycle data register hit
    wire ccyc_hit = ({wb_addr_in[11:2], 2'b00} == `CNF_DATA_ADDR) ;
    wire iack_hit = ({wb_addr_in[11:2], 2'b00} == `INT_ACK_ADDR) ;
`endif
`endif

// configuration read enable - supplied for host and guest bridges
reg conf_renable ;
assign wb_conf_renable_out = conf_renable ;

// wire for write attempt - 1 when external WB master is attempting a write
wire wattempt = ( CYC_I && STB_I && WE_I ) ; // write is qualified when cycle, strobe and write enable inputs are all high

// wire for read attempt - 1 when external WB master is attempting a read
wire rattempt = ( CYC_I && STB_I && ~WE_I ) ; // read is qualified when cycle and strobe are high and write enable is low

// burst access indicator
wire burst_transfer = CYC_I && CAB_I ;

// address allignement indicator
wire alligned_address = wb_addr_in[1:0] == 2'b00 ;

// SEL_I error indicator for IO and configuration accesses - select lines must be alligned with address
reg sel_error ;
always@(wb_addr_in or SEL_I)
begin
    case (wb_addr_in[1:0]) 
        2'b00: sel_error <= ~SEL_I[0] ; // select 0 must be 1, all others are don't cares.
        2'b01: sel_error <= ~SEL_I[1] || SEL_I[0]  ; // byte 0 can't be selected, byte 1 must be selected
        2'b10: sel_error <= ~SEL_I[2] || SEL_I[1] || SEL_I[0] ; // bytes 0 and 1 can't be selected, byte 2 must be selected
        2'b11: sel_error <= ~SEL_I[3] || SEL_I[2] || SEL_I[1] || SEL_I[0] ; // bytes 0, 1 and 2 can't be selected, byte 3 must be selected
    endcase
end

// WBW_FIFO control output
reg [3:0] wbw_fifo_control ;
assign wbw_fifo_control_out = wbw_fifo_control ; //control bus output for WBW_FIFO

// WBW_FIFO wenable output assignment
reg wbw_fifo_wenable ;
assign wbw_fifo_wenable_out = wbw_fifo_wenable ; //write enable for WBW_FIFO

// WBR_FIFO control outputs
reg wbr_fifo_flush, wbr_fifo_renable ; // flush and read enable outputs
assign wbr_fifo_renable_out = wbr_fifo_renable ; //read enable for wbr_fifo
assign wbr_fifo_flush_out   = wbr_fifo_flush ; // flush for wbr_fifo

// delayed transaction request control signals
reg del_req, del_done ;
assign del_req_out  = del_req ; // read request
assign del_done_out = del_done ; // read done
                    
// WISHBONE handshaking control outputs
reg ack, rty, err ;
assign ACK_O = ack ;
assign RTY_O = rty ;
assign ERR_O = err ;

/*----------------------------------------------------------------------------------------------------------------------
Control logic for image hits
img_hit - state of wb_hit_in bus when first data is acknowledged
same_hit - comparator output that compares first data phase's wb_hit_input and current wb_hit_input
---------------------------------------------------------------------------------------------------------------------*/
reg [4:0] img_hit ;

wire hit_latch_en = ( c_state == S_IDLE ) && ack ;

always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
        img_hit <= #`FF_DELAY 5'h00 ;
    else
        if (hit_latch_en)
            img_hit <= #`FF_DELAY wb_hit_in ;
end

wire same_hit  = ( img_hit == wb_hit_in ) ;

/*----------------------------------------------------------------------------------------------------------------------
Control logic for image control signals
pref_en - prefetch enable of currently selected image
mrl_en  - Memory read line enable of currently selected image
map     - Address space mapping for currently selected image
---------------------------------------------------------------------------------------------------------------------*/
reg pref_en, mrl_en, map ;

// hit error indicator
reg hit_error ;

always@(wb_hit_in or wb_pref_en_in or wb_mrl_en_in or wb_map_in)
begin
    case (wb_hit_in)
        5'h01:  begin
                    pref_en   <= wb_pref_en_in[0] ;
                    mrl_en    <= wb_mrl_en_in[0] ;
                    map       <= wb_map_in[0] ;
                    hit_error <= 1'b0 ;
                end
        
        5'h02:  begin
                   pref_en   <= wb_pref_en_in[1] ;
                   mrl_en    <= wb_mrl_en_in[1] ;
                   map       <= wb_map_in[1] ;
                   hit_error <= 1'b0 ;
                end

        5'h04:  begin
                    pref_en   <= wb_pref_en_in[2] ;
                    mrl_en    <= wb_mrl_en_in[2] ;
                    map       <= wb_map_in[2] ;
                    hit_error <= 1'b0 ;
                end
    
        5'h08:  begin
                    pref_en   <= wb_pref_en_in[3] ;
                    mrl_en    <= wb_mrl_en_in[3] ;
                    map       <= wb_map_in[3] ;
                    hit_error <= 1'b0 ;
                end

        5'h10:  begin
                    pref_en   <= wb_pref_en_in[4] ;
                    mrl_en    <= wb_mrl_en_in[4] ;
                    map       <= wb_map_in[4] ;
                    hit_error <= 1'b0 ;
                end

        default:begin
                    pref_en <= 1'b0 ;
                    mrl_en  <= 1'b0 ;
                    map     <= 1'b0 ;
                    hit_error <= |(wb_hit_in) ;
                end
    endcase     
end

assign del_burst_out = CAB_I && pref_en && ~WE_I; // delayed burst indicator - only when WB master attempts CAB transfer and prefetch enable of corresponding image is set - 
                                                  // applies for reads only - delayed write cannot be a burst

/*----------------------------------------------------------------------------------------------------------------------
Delayed transaction bus command generation
Bus command for delayed reads depends on image's address space mapping and control bits and
whether or not these are interrupt acknowledge requests or configuration cycle requests
---------------------------------------------------------------------------------------------------------------------*/
assign del_bc_out = del_bc ;

always@(map or CAB_I or mrl_en or pref_en or iack_hit or ccyc_hit or WE_I or wb_conf_hit_in)
begin
    `ifdef HOST
    if (wb_conf_hit_in)
    begin
        if (iack_hit)
        begin
            del_bc <= `BC_IACK ;
        end
        else
        begin
            if (WE_I)
                del_bc <= `BC_CONF_WRITE ;
            else
                del_bc <= `BC_CONF_READ ;
        end
    end
    else
    `endif
    begin
	    if (map) // map = 1 - IO space
	    begin
		    del_bc <= `BC_IO_READ ;
	    end
	    else 
	    if ( CAB_I && mrl_en && pref_en) // burst and memory read line enable
	    begin
		    del_bc <= `BC_MEM_READ_LN ;
	    end
	    else // normal single memory access
	    begin
		    del_bc <= `BC_MEM_READ ;
	    end
    end
end

// WISHBONE data output select lines for output multiplexor
reg sdata_o_sel ;

reg del_in_progress_out ; // state machine indicates whether current read completion is in progress on WISHBONE bus

// state machine logic
always@(
        c_state                     or 
        wattempt                    or
        img_wallow                  or
        burst_transfer              or 
        wb_hit_in                   or 
        map                         or 
        same_hit                    or
        alligned_address            or
        rattempt                    or
        do_dread_request            or
        do_dread_completion         or
        wbr_fifo_almost_empty_in    or
        wbr_fifo_control_in         or