delayed_write_reg.v

PCI IP核功能实现

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "delayed_write_reg.v"                             ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - [e-mail]                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.pdf   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, [e-mail]          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
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//// the original copyright notice and the associated disclaimer. ////
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//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
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//// later version.                                               ////
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//// details.                                                     ////
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//// You should have received a copy of the GNU Lesser General    ////
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//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: delayed_write_reg.v,v $
// Revision 1.1  2001/07/19 09:51:16  mihad
// Only delayed write storage is provided after merging delayed requests.
// All delayed reads now pass through FIFO.
//
//

`include "constants.v"
module DELAYED_WRITE_REG
(
	reset_in,
	req_clk_in,
	comp_wdata_out,
	req_we_in,
	req_wdata_in
);

// system inputs
input reset_in,
	  req_clk_in ; // request clock input

output [31:0] comp_wdata_out ; // data output

input req_we_in ; // write enable input
input [31:0] req_wdata_in ; // data input - latched with posedge of req_clk_in when req_we_in is high

reg [31:0] comp_wdata_out ;

// write request operation
always@(posedge req_clk_in or posedge reset_in)
begin
	if (reset_in)
		comp_wdata_out <= #`FF_DELAY 32'h0000_0000 ;
	else
	if (req_we_in)
		comp_wdata_out <= #`FF_DELAY req_wdata_in ;
end

endmodule // IACK_STORAGE