conf_space.v

PCI IP核功能实现

`ifdef	PCI_IMAGE4
		pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_12 or pci_ba2_bit0 or 
		pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_12 or pci_ba3_bit0 or 
		pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_12 or pci_ba4_bit0 or 
`endif
`ifdef	PCI_IMAGE5
		pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_12 or pci_ba2_bit0 or 
		pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_12 or pci_ba3_bit0 or 
		pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_12 or pci_ba4_bit0 or 
		pci_img_ctrl5_bit2_1 or pci_am5 or pci_ta5 or pci_ba5_bit31_12 or pci_ba5_bit0 or 
`endif
`ifdef	PCI_IMAGE6
		pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_12 or pci_ba2_bit0 or 
		pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_12 or pci_ba3_bit0 or 
		pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_12 or pci_ba4_bit0 or 
		pci_img_ctrl5_bit2_1 or pci_am5 or pci_ta5 or pci_ba5_bit31_12 or pci_ba5_bit0 or 
`endif
		interrupt_line or 
		pci_err_cs_bit31_24 or pci_err_cs_bit10 or pci_err_cs_bit8 or pci_err_cs_bit0 or 
		pci_err_addr or pci_err_data or 
		wb_img_ctrl1_bit2_0 or wb_ba1_bit31_12 or wb_ba1_bit0 or wb_am1 or wb_ta1 or 
`ifdef	WB_IMAGE2
		wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or 
`endif
`ifdef	WB_IMAGE3
		wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or 
		wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or 
`endif
`ifdef	WB_IMAGE4
		wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or 
		wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or 
		wb_img_ctrl4_bit2_0 or wb_ba4_bit31_12 or wb_ba4_bit0 or wb_am4 or wb_ta4 or 
`endif
`ifdef	WB_IMAGE5
		wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or 
		wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or 
		wb_img_ctrl4_bit2_0 or wb_ba4_bit31_12 or wb_ba4_bit0 or wb_am4 or wb_ta4 or 
		wb_img_ctrl5_bit2_0 or wb_ba5_bit31_12 or wb_ba5_bit0 or wb_am5 or wb_ta5 or 
`endif
		wb_err_cs_bit31_24 or wb_err_cs_bit10_8 or wb_err_cs_bit0 or wb_err_addr or wb_err_data or 
		cnf_addr_bit23_2 or cnf_addr_bit0 or icr_bit31 or icr_bit3_0 or isr_bit3_0
		)  
begin                       
	if ((conf_hit == 1'b1) & (w_re == 1'b1))
	begin               
		case (w_conf_address_in)
			// PCI header - configuration space
			12'h000: w_conf_data_out = #`FF_DELAY { r_device_id, r_vendor_id } ;
			12'h004: w_conf_data_out = #`FF_DELAY { status_bit15_11, r_status_bit10_9, status_bit8, 2'h0, r_status_bit5, 
										 5'h00, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ;
			12'h008: w_conf_data_out = #`FF_DELAY { r_class_code, r_revision_id } ;
			12'h00c: w_conf_data_out = #`FF_DELAY { 8'h00, r_header_type, latency_timer, cache_line_size_reg } ;
			12'h010: w_conf_data_out = #`FF_DELAY { pci_ba0_bit31_12, 11'h000, pci_ba0_bit0 } & { pci_am0[31:12], 12'h001 } ;
			12'h014: w_conf_data_out = #`FF_DELAY { pci_ba1_bit31_12, 11'h000, pci_ba1_bit0 } & { pci_am1[31:12], 12'h001 } ;
			12'h018: w_conf_data_out = #`FF_DELAY { pci_ba2_bit31_12, 11'h000, pci_ba2_bit0 } & { pci_am2[31:12], 12'h001 } ;
			12'h01c: w_conf_data_out = #`FF_DELAY { pci_ba3_bit31_12, 11'h000, pci_ba3_bit0 } & { pci_am3[31:12], 12'h001 } ;
			12'h020: w_conf_data_out = #`FF_DELAY { pci_ba4_bit31_12, 11'h000, pci_ba4_bit0 } & { pci_am4[31:12], 12'h001 } ;
			12'h024: w_conf_data_out = #`FF_DELAY { pci_ba5_bit31_12, 11'h000, pci_ba5_bit0 } & { pci_am5[31:12], 12'h001 } ;
			12'h03c: w_conf_data_out = #`FF_DELAY { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ;
			// PCI target - configuration space
			`P_IMG_CTRL0_ADDR: w_conf_data_out = #`FF_DELAY { 29'h00000000, pci_img_ctrl0_bit2_1, 1'h0 } ;
            `P_BA0_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_ba0_bit31_12, 11'h000, pci_ba0_bit0 } & { pci_am0[31:12], 12'h001 } ;
            `P_AM0_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_am0, 12'h000 } ;
            `P_TA0_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_ta0, 12'h000 } ;
            `P_IMG_CTRL1_ADDR: w_conf_data_out = #`FF_DELAY { 29'h00000000, pci_img_ctrl1_bit2_1, 1'h0 } ;
            `P_BA1_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_ba1_bit31_12, 11'h000, pci_ba1_bit0 } & { pci_am1[31:12], 12'h001 } ;
            `P_AM1_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_am1, 12'h000 } ;
            `P_TA1_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_ta1, 12'h000 } ;
            `P_IMG_CTRL2_ADDR: w_conf_data_out = #`FF_DELAY { 29'h00000000, pci_img_ctrl2_bit2_1, 1'h0 } ;
            `P_BA2_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_ba2_bit31_12, 11'h000, pci_ba2_bit0 } & { pci_am2[31:12], 12'h001 } ;
            `P_AM2_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_am2, 12'h000 } ;
            `P_TA2_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_ta2, 12'h000 } ;
            `P_IMG_CTRL3_ADDR: w_conf_data_out = #`FF_DELAY { 29'h00000000, pci_img_ctrl3_bit2_1, 1'h0 } ;
            `P_BA3_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_ba3_bit31_12, 11'h000, pci_ba3_bit0 } & { pci_am3[31:12], 12'h001 } ;
            `P_AM3_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_am3, 12'h000 } ;
            `P_TA3_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_ta3, 12'h000 } ;
            `P_IMG_CTRL4_ADDR: w_conf_data_out = #`FF_DELAY { 29'h00000000, pci_img_ctrl4_bit2_1, 1'h0 } ;
            `P_BA4_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_ba4_bit31_12, 11'h000, pci_ba4_bit0 } & { pci_am4[31:12], 12'h001 } ;
            `P_AM4_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_am4, 12'h000 } ;
            `P_TA4_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_ta4, 12'h000 } ;
            `P_IMG_CTRL5_ADDR: w_conf_data_out = #`FF_DELAY { 29'h00000000, pci_img_ctrl5_bit2_1, 1'h0 } ;
            `P_BA5_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_ba5_bit31_12, 11'h000, pci_ba5_bit0 } & { pci_am5[31:12], 12'h001 } ;
            `P_AM5_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_am5, 12'h000 } ;
            `P_TA5_ADDR		 : w_conf_data_out = #`FF_DELAY { pci_ta5, 12'h000 } ;
            `P_ERR_CS_ADDR	 : w_conf_data_out = #`FF_DELAY { pci_err_cs_bit31_24, 13'h0000, pci_err_cs_bit10, 1'h0, 
            									   pci_err_cs_bit8, 7'h00, pci_err_cs_bit0 } ;
            `P_ERR_ADDR_ADDR : w_conf_data_out = #`FF_DELAY pci_err_addr ;
            `P_ERR_DATA_ADDR : w_conf_data_out = #`FF_DELAY pci_err_data ;
			// WB slave - configuration space
			`WB_CONF_SPC_BAR_ADDR: w_conf_data_out = #`FF_DELAY { wb_ba0_bit31_12, 11'h000, wb_ba0_bit0 } ;
			`W_IMG_CTRL1_ADDR: w_conf_data_out = #`FF_DELAY { 29'h00000000, wb_img_ctrl1_bit2_0 } ;
			`W_BA1_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_ba1_bit31_12, 11'h000, wb_ba1_bit0 } & { wb_am1[31:12], 12'h001 } ;                                        
			`W_AM1_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_am1, 12'h000 } ;                                                               
			`W_TA1_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_ta1, 12'h000 } ;                                                               
			`W_IMG_CTRL2_ADDR: w_conf_data_out = #`FF_DELAY { 29'h00000000, wb_img_ctrl2_bit2_0 } ;
			`W_BA2_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_ba2_bit31_12, 11'h000, wb_ba2_bit0 } & { wb_am2[31:12], 12'h001 } ;                                        
			`W_AM2_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_am2, 12'h000 } ;                                                               
			`W_TA2_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_ta2, 12'h000 } ;                                                               
			`W_IMG_CTRL3_ADDR: w_conf_data_out = #`FF_DELAY { 29'h00000000, wb_img_ctrl3_bit2_0 } ;
			`W_BA3_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_ba3_bit31_12, 11'h000, wb_ba3_bit0 } & { wb_am3[31:12], 12'h001 } ;                                        
			`W_AM3_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_am3, 12'h000 } ;                                                               
			`W_TA3_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_ta3, 12'h000 } ;                                                               
			`W_IMG_CTRL4_ADDR: w_conf_data_out = #`FF_DELAY { 29'h00000000, wb_img_ctrl4_bit2_0 } ;
			`W_BA4_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_ba4_bit31_12, 11'h000, wb_ba4_bit0 } & { wb_am4[31:12], 12'h001 } ;                                        
			`W_AM4_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_am4, 12'h000 } ;                                                               
			`W_TA4_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_ta4, 12'h000 } ;                                                               
			`W_IMG_CTRL5_ADDR: w_conf_data_out = #`FF_DELAY { 29'h00000000, wb_img_ctrl5_bit2_0 } ;
			`W_BA5_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_ba5_bit31_12, 11'h000, wb_ba5_bit0 } & { wb_am5[31:12], 12'h001 } ;
			`W_AM5_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_am5, 12'h000 } ;                       
			`W_TA5_ADDR		 : w_conf_data_out = #`FF_DELAY { wb_ta5, 12'h000 } ;                       
			`W_ERR_CS_ADDR	 : w_conf_data_out = #`FF_DELAY { wb_err_cs_bit31_24, 13'h0000, wb_err_cs_bit10_8, 
            									   7'h00, wb_err_cs_bit0 } ;
			`W_ERR_ADDR_ADDR : w_conf_data_out = #`FF_DELAY wb_err_addr ;
			`W_ERR_DATA_ADDR : w_conf_data_out = #`FF_DELAY wb_err_data ;
			
			`CNF_ADDR_ADDR	 : w_conf_data_out = #`FF_DELAY { 8'h00, cnf_addr_bit23_2, 1'h0, cnf_addr_bit0 } ;
			// `CNF_DATA_ADDR: implemented elsewhere !!! 
			// `INT_ACK_ADDR : implemented elsewhere !!!
            `ICR_ADDR		 : w_conf_data_out = #`FF_DELAY { icr_bit31, 27'h0000_000, icr_bit3_0 } ;
            `ISR_ADDR		 : w_conf_data_out = #`FF_DELAY { 28'h0000_000, isr_bit3_0 } ;
                               
			default	: w_conf_data_out = 32'h0000_0000 ;
		endcase
	end 
	else
		w_conf_data_out = 32'h0000_0000 ;
end

always@(posedge w_clock or posedge reset)     
begin         
	// Here are implemented all registers that are reset with RESET signal otherwise they can be normaly written!!!
	// Registers that are commented are implemented after this alwasy statement, because they are e.g. reset with
	//   RESET signal, set with some status signal and they are erased with writting '1' into them !!!
	if (reset)
	begin
		/*status_bit15_11 ; status_bit8 ;*/ command_bit8 <= 1'h0 ; command_bit6 <= 1'h0 ; command_bit2_0 <= 3'h0 ;
		latency_timer <= 8'h00 ; cache_line_size_reg <= 8'h00 ;
		// ALL pci_base address registers are the same as pci_baX registers !
		interrupt_line <= 8'h00 ;

		`ifdef	HOST
		 `ifdef	PCI_IMAGE6	// if PCI bridge is HOST and IMAGE0 is assigned as general image space
					pci_img_ctrl0_bit2_1 <= 2'h0 ;
		//			pci_ba0_bit31_12 is always a register (never parameter) !!! 
					pci_ba0_bit0 <= 1'h0 ; 
					pci_am0 <= def_pci_image0_addr_map ;
					pci_ta0 <= 20'h0000_0 ;
		 `endif
		`endif
		pci_ba0_bit31_12 <= 20'h0000_0 ; 
		
		pci_img_ctrl1_bit2_1 <= 2'h0 ;
		pci_ba1_bit31_12 <= 20'h0000_0 ; pci_ba1_bit0 <= 1'h0 ;
		pci_am1 <= def_pci_image1_addr_map ;
		pci_ta1 <= 20'h0000_0 ;
		`ifdef	PCI_IMAGE2
        			pci_img_ctrl2_bit2_1 <= 2'h0 ;
					pci_ba2_bit31_12 <= 20'h0000_0 ; pci_ba2_bit0 <= 1'h0 ;
					pci_am2 <= def_pci_image2_addr_map ;
					pci_ta2 <= 20'h0000_0 ;
		`endif
		`ifdef	PCI_IMAGE3
        			pci_img_ctrl2_bit2_1 <= 2'h0 ;
					pci_ba2_bit31_12 <= 20'h0000_0 ; pci_ba2_bit0 <= 1'h0 ;
					pci_am2 <= def_pci_image2_addr_map ;
					pci_ta2 <= 20'h0000_0 ;
					pci_img_ctrl3_bit2_1 <= 2'h0 ;
        			pci_ba3_bit31_12 <= 20'h0000_0 ; pci_ba3_bit0 <= 1'h0 ;
        			pci_am3 <= def_pci_image3_addr_map ;
					pci_ta3 <= 20'h0000_0 ;
		`endif
		`ifdef	PCI_IMAGE4
        			pci_img_ctrl2_bit2_1 <= 2'h0 ;
					pci_ba2_bit31_12 <= 20'h0000_0 ; pci_ba2_bit0 <= 1'h0 ;
					pci_am2 <= def_pci_image2_addr_map ;
					pci_ta2 <= 20'h0000_0 ;
					pci_img_ctrl3_bit2_1 <= 2'h0 ;
        			pci_ba3_bit31_12 <= 20'h0000_0 ; pci_ba3_bit0 <= 1'h0 ;
        			pci_am3 <= def_pci_image3_addr_map ;
					pci_ta3 <= 20'h0000_0 ;
					pci_img_ctrl4_bit2_1 <= 2'h0 ;
					pci_ba4_bit31_12 <= 20'h0000_0 ; pci_ba4_bit0 <= 1'h0 ;
					pci_am4 <= def_pci_image4_addr_map ;
					pci_ta4 <= 20'h0000_0 ;
		`endif
		`ifdef	PCI_IMAGE5
        			pci_img_ctrl2_bit2_1 <= 2'h0 ;
					pci_ba2_bit31_12 <= 20'h0000_0 ; pci_ba2_bit0 <= 1'h0 ;
					pci_am2 <= def_pci_image2_addr_map ;
					pci_ta2 <= 20'h0000_0 ;
					pci_img_ctrl3_bit2_1 <= 2'h0 ;
        			pci_ba3_bit31_12 <= 20'h0000_0 ; pci_ba3_bit0 <= 1'h0 ;
        			pci_am3 <= def_pci_image3_addr_map ;
					pci_ta3 <= 20'h0000_0 ;
					pci_img_ctrl4_bit2_1 <= 2'h0 ;
					pci_ba4_bit31_12 <= 20'h0000_0 ; pci_ba4_bit0 <= 1'h0 ;
					pci_am4 <= def_pci_image4_addr_map ;
					pci_ta4 <= 20'h0000_0 ;
					pci_img_ctrl5_bit2_1 <= 2'h0 ;
					pci_ba5_bit31_12 <= 20'h0000_0 ; pci_ba5_bit0 <= 1'h0 ;
					pci_am5 <= def_pci_image5_addr_map ;
					pci_ta5 <= 20'h0000_0 ;
		`endif
		`ifdef	PCI_IMAGE6
        			pci_img_ctrl2_bit2_1 <= 2'h0 ;
					pci_ba2_bit31_12 <= 20'h0000_0 ; pci_ba2_bit0 <= 1'h0 ;
					pci_am2 <= def_pci_image2_addr_map ;
					pci_ta2 <= 20'h0000_0 ;
					pci_img_ctrl3_bit2_1 <= 2'h0 ;
        			pci_ba3_bit31_12 <= 20'h0000_0 ; pci_ba3_bit0 <= 1'h0 ;
        			pci_am3 <= def_pci_image3_addr_map ;
					pci_ta3 <= 20'h0000_0 ;
					pci_img_ctrl4_bit2_1 <= 2'h0 ;
					pci_ba4_bit31_12 <= 20'h0000_0 ; pci_ba4_bit0 <= 1'h0 ;
					pci_am4 <= def_pci_image4_addr_map ;
					pci_ta4 <= 20'h0000_0 ;
					pci_img_ctrl5_bit2_1 <= 2'h0 ;
					pci_ba5_bit31_12 <= 20'h0000_0 ; pci_ba5_bit0 <= 1'h0 ;
					pci_am5 <= def_pci_image5_addr_map ;
					pci_ta5 <= 20'h0000_0 ;
		`endif
		/*pci_err_cs_bit31_24 ; pci_err_cs_bit10 ; pci_err_cs_bit8 ;*/ pci_err_cs_bit0 <= 1'h0 ;
		/*pci_err_addr ;*/
        /*pci_err_data ;*/
		// 
		wb_img_ctrl1_bit2_0 <= 3'h0 ;
		wb_ba1_bit31_12 <= 20'h0000_0 ; wb_ba1_bit0 <= 1'h0 ;
		wb_am1 <= def_wb_image1_addr_map ;
		wb_ta1 <= 20'h0000_0 ;
        `ifdef	WB_IMAGE2
					wb_img_ctrl2_bit2_0 <= 3'h0 ;
					wb_ba2_bit31_12 <= 20'h0000_0 ; wb_ba2_bit0 <= 1'h0 ;
					wb_am2 <