conf_space.v

PCI IP核功能实现

			parameter			wb_image4 = 1 ; 
			reg		[2 : 0]		wb_img_ctrl4_bit2_0 ;
			reg		[31 : 12]	wb_ba4_bit31_12 ;
			reg					wb_ba4_bit0 ;
			reg		[31 : 12]	wb_am4 ;
			reg		[31 : 12]	wb_ta4 ;

			parameter			wb_image5 = 1 ; 
			reg		[2 : 0]		wb_img_ctrl5_bit2_0 ;
			reg		[31 : 12]	wb_ba5_bit31_12 ;
			reg					wb_ba5_bit0 ;
			reg		[31 : 12]	wb_am5 ;
			reg		[31 : 12]	wb_ta5 ;
`endif                         
			reg		[31 : 24]	wb_err_cs_bit31_24 ;
			reg		[10 : 8]	wb_err_cs_bit10_8 ;
			reg					wb_err_cs_bit0 ;
			reg		[31 : 0]	wb_err_addr ;
			reg		[31 : 0]	wb_err_data ;
                                
                                
/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
Configuration Cycle address register
	There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to 
	sign which bit or range of bits are implemented. 
-------------------------------------------------------------------------------------------------------------
###########################################################################################################*/
                                
/*-----------------------------------------------------------------------------------------------------------
[860h-868h]                     
	PCI bridge must ignore Type 1 configuration cycles (Master Abort) since they are used for PCI to PCI 
	bridges. This is single function device, that means responding on configuration cycles to all functions 
	(or responding only to function 0). Configuration address register for generating configuration cycles 
	is prepared for all options (it includes Bus Number, Device, Function, Offset and Type).
	Interrupt acknowledge register stores interrupt vector data returned during Interrupt Acknowledge cycle.
-----------------------------------------------------------------------------------------------------------*/
			reg		[23 : 2]	cnf_addr_bit23_2 ;
			reg					cnf_addr_bit0 ;
			// reg	[31 : 0]	cnf_data ;		IMPLEMENTED elsewhere !!!!!
			// reg	[31 : 0]	int_ack ;		IMPLEMENTED elsewhere !!!!!
                                
                                
/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
General Interrupt registers     
	There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to 
	sign which bit or range of bits are implemented. 
-------------------------------------------------------------------------------------------------------------
###########################################################################################################*/
                                
/*-----------------------------------------------------------------------------------------------------------
[FF8h-FFCh]                     
	Bit 31 in the Interrupt Control register is set by software and used to generate SOFT RESET. Other 4
	bits are used to enable interrupt generations.
	4 LSbits in the Interrupt Status register are indicating System Error Int, Parity Error Int, Error
	Int and Inerrupt respecively.
-----------------------------------------------------------------------------------------------------------*/
			reg					icr_bit31 ;
			reg		[3 : 0]		icr_bit3_0 ;
			reg		[3 : 0]		isr_bit3_0 ;
        
                                
/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------


-----------------------------------------------------------------------------------------------------------*/
                                
always@(r_re or 
		conf_hit or 
		r_conf_address_in or
		status_bit15_11 or status_bit8 or command_bit8 or command_bit6 or command_bit2_0 or
		latency_timer or cache_line_size_reg or 
		pci_ba0_bit31_12 or // always a register
`ifdef	HOST
 `ifdef	PCI_IMAGE6	// if PCI bridge is HOST and IMAGE0 is assigned as general image space
		pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or  
 `endif
`endif
		pci_img_ctrl1_bit2_1 or pci_am1 or pci_ta1 or pci_ba1_bit31_12 or pci_ba1_bit0 or 
`ifdef	PCI_IMAGE2
		pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_12 or pci_ba2_bit0 or 
`endif
`ifdef	PCI_IMAGE3
		pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_12 or pci_ba2_bit0 or 
		pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_12 or pci_ba3_bit0 or 
`endif
`ifdef	PCI_IMAGE4
		pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_12 or pci_ba2_bit0 or 
		pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_12 or pci_ba3_bit0 or 
		pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_12 or pci_ba4_bit0 or 
`endif
`ifdef	PCI_IMAGE5
		pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_12 or pci_ba2_bit0 or 
		pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_12 or pci_ba3_bit0 or 
		pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_12 or pci_ba4_bit0 or 
		pci_img_ctrl5_bit2_1 or pci_am5 or pci_ta5 or pci_ba5_bit31_12 or pci_ba5_bit0 or 
`endif
`ifdef	PCI_IMAGE6
		pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_12 or pci_ba2_bit0 or 
		pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_12 or pci_ba3_bit0 or 
		pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_12 or pci_ba4_bit0 or 
		pci_img_ctrl5_bit2_1 or pci_am5 or pci_ta5 or pci_ba5_bit31_12 or pci_ba5_bit0 or 
`endif
		interrupt_line or 
		pci_err_cs_bit31_24 or pci_err_cs_bit10 or pci_err_cs_bit8 or pci_err_cs_bit0 or 
		pci_err_addr or pci_err_data or 
		wb_img_ctrl1_bit2_0 or wb_ba1_bit31_12 or wb_ba1_bit0 or wb_am1 or wb_ta1 or 
`ifdef	WB_IMAGE2
		wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or 
`endif
`ifdef	WB_IMAGE3
		wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or 
		wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or 
`endif
`ifdef	WB_IMAGE4
		wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or 
		wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or 
		wb_img_ctrl4_bit2_0 or wb_ba4_bit31_12 or wb_ba4_bit0 or wb_am4 or wb_ta4 or wb_am5 or // !!!!!!!!!!!!!!!!!!!!!
`endif
`ifdef	WB_IMAGE5
		wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or 
		wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or 
		wb_img_ctrl4_bit2_0 or wb_ba4_bit31_12 or wb_ba4_bit0 or wb_am4 or wb_ta4 or 
		wb_img_ctrl5_bit2_0 or wb_ba5_bit31_12 or wb_ba5_bit0 or wb_am5 or wb_ta5 or 
`endif
		wb_err_cs_bit31_24 or wb_err_cs_bit10_8 or wb_err_cs_bit0 or wb_err_addr or wb_err_data or 
		cnf_addr_bit23_2 or cnf_addr_bit0 or icr_bit31 or icr_bit3_0 or isr_bit3_0
		)     
begin                       
	if ((conf_hit == 1'b1) & (r_re == 1'b1))
	begin               
		case (r_conf_address_in)
			// PCI header - configuration space
			12'h000: r_conf_data_out = #`FF_DELAY { r_device_id, r_vendor_id } ;
			12'h004: r_conf_data_out = #`FF_DELAY { status_bit15_11, r_status_bit10_9, status_bit8, 2'h0, r_status_bit5, 
										 5'h00, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ;
			12'h008: r_conf_data_out = #`FF_DELAY { r_class_code, r_revision_id } ;
			12'h00c: r_conf_data_out = #`FF_DELAY { 8'h00, r_header_type, latency_timer, cache_line_size_reg } ;
			12'h010: r_conf_data_out = #`FF_DELAY { pci_ba0_bit31_12, 11'h000, pci_ba0_bit0 } & { pci_am0[31:12], 12'h001 } ;
			12'h014: r_conf_data_out = #`FF_DELAY { pci_ba1_bit31_12, 11'h000, pci_ba1_bit0 } & { pci_am1[31:12], 12'h001 } ;                            
			12'h018: r_conf_data_out = #`FF_DELAY { pci_ba2_bit31_12, 11'h000, pci_ba2_bit0 } & { pci_am2[31:12], 12'h001 } ;
			12'h01c: r_conf_data_out = #`FF_DELAY { pci_ba3_bit31_12, 11'h000, pci_ba3_bit0 } & { pci_am3[31:12], 12'h001 } ;                            
			12'h020: r_conf_data_out = #`FF_DELAY { pci_ba4_bit31_12, 11'h000, pci_ba4_bit0 } & { pci_am4[31:12], 12'h001 } ;
			12'h024: r_conf_data_out = #`FF_DELAY { pci_ba5_bit31_12, 11'h000, pci_ba5_bit0 } & { pci_am5[31:12], 12'h001 } ;
			12'h03c: r_conf_data_out = #`FF_DELAY { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ;
			// PCI target - configuration space
			`P_IMG_CTRL0_ADDR: r_conf_data_out = #`FF_DELAY { 29'h00000000, pci_img_ctrl0_bit2_1, 1'h0 } ;
            `P_BA0_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_ba0_bit31_12, 11'h000, pci_ba0_bit0 } & { pci_am0[31:12], 12'h001 } ;
            `P_AM0_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_am0, 12'h000 } ;
            `P_TA0_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_ta0, 12'h000 } ;
            `P_IMG_CTRL1_ADDR: r_conf_data_out = #`FF_DELAY { 29'h00000000, pci_img_ctrl1_bit2_1, 1'h0 } ;
            `P_BA1_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_ba1_bit31_12, 11'h000, pci_ba1_bit0 } & { pci_am1[31:12], 12'h001 } ;
            `P_AM1_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_am1, 12'h000 } ;
            `P_TA1_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_ta1, 12'h000 } ;
            `P_IMG_CTRL2_ADDR: r_conf_data_out = #`FF_DELAY { 29'h00000000, pci_img_ctrl2_bit2_1, 1'h0 } ;
            `P_BA2_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_ba2_bit31_12, 11'h000, pci_ba2_bit0 } & { pci_am2[31:12], 12'h001 } ;
            `P_AM2_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_am2, 12'h000 } ;
            `P_TA2_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_ta2, 12'h000 } ;
            `P_IMG_CTRL3_ADDR: r_conf_data_out = #`FF_DELAY { 29'h00000000, pci_img_ctrl3_bit2_1, 1'h0 } ;
            `P_BA3_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_ba3_bit31_12, 11'h000, pci_ba3_bit0 } & { pci_am3[31:12], 12'h001 } ;
            `P_AM3_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_am3, 12'h000 } ;
            `P_TA3_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_ta3, 12'h000 } ;
            `P_IMG_CTRL4_ADDR: r_conf_data_out = #`FF_DELAY { 29'h00000000, pci_img_ctrl4_bit2_1, 1'h0 } ;
            `P_BA4_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_ba4_bit31_12, 11'h000, pci_ba4_bit0 } & { pci_am4[31:12], 12'h001 } ;
            `P_AM4_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_am4, 12'h000 } ;
            `P_TA4_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_ta4, 12'h000 } ;
            `P_IMG_CTRL5_ADDR: r_conf_data_out = #`FF_DELAY { 29'h00000000, pci_img_ctrl5_bit2_1, 1'h0 } ;
            `P_BA5_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_ba5_bit31_12, 11'h000, pci_ba5_bit0 } & { pci_am5[31:12], 12'h001 } ;
            `P_AM5_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_am5, 12'h000 } ;
            `P_TA5_ADDR		 : r_conf_data_out = #`FF_DELAY { pci_ta5, 12'h000 } ;
            `P_ERR_CS_ADDR	 : r_conf_data_out = #`FF_DELAY { pci_err_cs_bit31_24, 13'h0000, pci_err_cs_bit10, 1'h0, 
            									   pci_err_cs_bit8, 7'h00, pci_err_cs_bit0 } ;
            `P_ERR_ADDR_ADDR : r_conf_data_out = #`FF_DELAY pci_err_addr ;
            `P_ERR_DATA_ADDR : r_conf_data_out = #`FF_DELAY pci_err_data ;
			// WB slave - configuration space
			`WB_CONF_SPC_BAR_ADDR: r_conf_data_out = #`FF_DELAY { wb_ba0_bit31_12, 11'h000, wb_ba0_bit0 } ;
			`W_IMG_CTRL1_ADDR: r_conf_data_out = #`FF_DELAY { 29'h00000000, wb_img_ctrl1_bit2_0 } ;
			`W_BA1_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_ba1_bit31_12, 11'h000, wb_ba1_bit0 } & { wb_am1[31:12], 12'h001 } ;                                        
			`W_AM1_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_am1, 12'h000 } ;                                                               
			`W_TA1_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_ta1, 12'h000 } ;                                                               
			`W_IMG_CTRL2_ADDR: r_conf_data_out = #`FF_DELAY { 29'h00000000, wb_img_ctrl2_bit2_0 } ;
			`W_BA2_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_ba2_bit31_12, 11'h000, wb_ba2_bit0 } & { wb_am2[31:12], 12'h001 } ;                                        
			`W_AM2_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_am2, 12'h000 } ;                                                               
			`W_TA2_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_ta2, 12'h000 } ;                                                               
			`W_IMG_CTRL3_ADDR: r_conf_data_out = #`FF_DELAY { 29'h00000000, wb_img_ctrl3_bit2_0 } ;
			`W_BA3_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_ba3_bit31_12, 11'h000, wb_ba3_bit0 } & { wb_am3[31:12], 12'h001 } ;                                        
			`W_AM3_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_am3, 12'h000 } ;                                                               
			`W_TA3_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_ta3, 12'h000 } ;                                                               
			`W_IMG_CTRL4_ADDR: r_conf_data_out = #`FF_DELAY { 29'h00000000, wb_img_ctrl4_bit2_0 } ;
			`W_BA4_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_ba4_bit31_12, 11'h000, wb_ba4_bit0 } & { wb_am4[31:12], 12'h001 } ;                                        
			`W_AM4_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_am4, 12'h000 } ;                                                               
			`W_TA4_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_ta4, 12'h000 } ;                                                               
			`W_IMG_CTRL5_ADDR: r_conf_data_out = #`FF_DELAY { 29'h00000000, wb_img_ctrl5_bit2_0 } ;
			`W_BA5_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_ba5_bit31_12, 11'h000, wb_ba5_bit0 } & { wb_am5[31:12], 12'h001 } ;
			`W_AM5_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_am5, 12'h000 } ;                       
			`W_TA5_ADDR		 : r_conf_data_out = #`FF_DELAY { wb_ta5, 12'h000 } ;                       
			`W_ERR_CS_ADDR	 : r_conf_data_out = #`FF_DELAY { wb_err_cs_bit31_24, 13'h0000, wb_err_cs_bit10_8, 
            									   7'h00, wb_err_cs_bit0 } ;
			`W_ERR_ADDR_ADDR : r_conf_data_out = #`FF_DELAY wb_err_addr ;
			`W_ERR_DATA_ADDR : r_conf_data_out = #`FF_DELAY wb_err_data ;
			
			`CNF_ADDR_ADDR	 : r_conf_data_out = #`FF_DELAY { 8'h00, cnf_addr_bit23_2, 1'h0, cnf_addr_bit0 } ;
			// `CNF_DATA_ADDR: implemented elsewhere !!! 
			// `INT_ACK_ADDR : implemented elsewhere !!!
            `ICR_ADDR		 : r_conf_data_out = #`FF_DELAY { icr_bit31, 27'h0000_000, icr_bit3_0 } ;
            `ISR_ADDR		 : r_conf_data_out = #`FF_DELAY { 28'h0000_000, isr_bit3_0 } ;
                               
			default	: r_conf_data_out = 32'h0000_0000 ;
		endcase
	end
	else
		r_conf_data_out = 32'h0000_0000 ;
end
	                   
always@(w_re or 
		conf_hit or 
		w_conf_address_in or
		status_bit15_11 or status_bit8 or command_bit8 or command_bit6 or command_bit2_0 or
		latency_timer or cache_line_size_reg or 
		pci_ba0_bit31_12 or // always a register
`ifdef	HOST
 `ifdef	PCI_IMAGE6	// if PCI bridge is HOST and IMAGE0 is assigned as general image space
		pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or  
 `endif
`endif
		pci_img_ctrl1_bit2_1 or pci_am1 or pci_ta1 or pci_ba1_bit31_12 or pci_ba1_bit0 or 
`ifdef	PCI_IMAGE2
		pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_12 or pci_ba2_bit0 or 
`endif
`ifdef	PCI_IMAGE3
		pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_12 or pci_ba2_bit0 or 
		pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_12 or pci_ba3_bit0 or 
`endif