conf_space.v

PCI IP核功能实现

`ifdef		PCI_IMAGE4 
			parameter			pci_image2 = 1 ;
			reg		[2 : 1]		pci_img_ctrl2_bit2_1 ;
			reg		[31 : 12]	pci_ba2_bit31_12 ;
			reg					pci_ba2_bit0 ;
			reg		[31 : 12]	pci_am2 ;
			reg		[31 : 12]	pci_ta2 ;

			parameter			pci_image3 = 1 ;
			reg		[2 : 1]		pci_img_ctrl3_bit2_1 ;
			reg		[31 : 12]	pci_ba3_bit31_12 ;
			reg					pci_ba3_bit0 ;
			reg		[31 : 12]	pci_am3 ;
			reg		[31 : 12]	pci_ta3 ;
            
			parameter			pci_image4 = 1 ;
			reg		[2 : 1]		pci_img_ctrl4_bit2_1 ;
			reg		[31 : 12]	pci_ba4_bit31_12 ;
			reg					pci_ba4_bit0 ;
			reg		[31 : 12]	pci_am4 ;
			reg		[31 : 12]	pci_ta4 ;

			parameter			pci_image5 = 0 ;
            wire	[2 : 1]		pci_img_ctrl5_bit2_1 = 2'b00 ;
			wire	[31 : 12]	pci_ba5_bit31_12 = 20'h0000_0 ;    
            wire				pci_ba5_bit0 = 1'b0 ;        
            wire	[31 : 12]	pci_am5 = 20'h0000_0 ;             
            wire	[31 : 12]	pci_ta5 = 20'h0000_0 ;             
`endif
`ifdef		PCI_IMAGE5              
			parameter			pci_image2 = 1 ;
			reg		[2 : 1]		pci_img_ctrl2_bit2_1 ;
			reg		[31 : 12]	pci_ba2_bit31_12 ;
			reg					pci_ba2_bit0 ;
			reg		[31 : 12]	pci_am2 ;
			reg		[31 : 12]	pci_ta2 ;

			parameter			pci_image3 = 1 ;
			reg		[2 : 1]		pci_img_ctrl3_bit2_1 ;
			reg		[31 : 12]	pci_ba3_bit31_12 ;
			reg					pci_ba3_bit0 ;
			reg		[31 : 12]	pci_am3 ;
			reg		[31 : 12]	pci_ta3 ;
            
			parameter			pci_image4 = 1 ;
			reg		[2 : 1]		pci_img_ctrl4_bit2_1 ;
			reg		[31 : 12]	pci_ba4_bit31_12 ;
			reg					pci_ba4_bit0 ;
			reg		[31 : 12]	pci_am4 ;
			reg		[31 : 12]	pci_ta4 ;

			parameter			pci_image5 = 1 ;
			reg		[2 : 1]		pci_img_ctrl5_bit2_1 ;
			reg		[31 : 12]	pci_ba5_bit31_12 ;
			reg					pci_ba5_bit0 ;
			reg		[31 : 12]	pci_am5 ;
			reg		[31 : 12]	pci_ta5 ;
`endif
`ifdef		PCI_IMAGE6              
			parameter			pci_image2 = 1 ;
			reg		[2 : 1]		pci_img_ctrl2_bit2_1 ;
			reg		[31 : 12]	pci_ba2_bit31_12 ;
			reg					pci_ba2_bit0 ;
			reg		[31 : 12]	pci_am2 ;
			reg		[31 : 12]	pci_ta2 ;

			parameter			pci_image3 = 1 ;
			reg		[2 : 1]		pci_img_ctrl3_bit2_1 ;
			reg		[31 : 12]	pci_ba3_bit31_12 ;
			reg					pci_ba3_bit0 ;
			reg		[31 : 12]	pci_am3 ;
			reg		[31 : 12]	pci_ta3 ;
            
			parameter			pci_image4 = 1 ;
			reg		[2 : 1]		pci_img_ctrl4_bit2_1 ;
			reg		[31 : 12]	pci_ba4_bit31_12 ;
			reg					pci_ba4_bit0 ;
			reg		[31 : 12]	pci_am4 ;
			reg		[31 : 12]	pci_ta4 ;

			parameter			pci_image5 = 1 ;
			reg		[2 : 1]		pci_img_ctrl5_bit2_1 ;
			reg		[31 : 12]	pci_ba5_bit31_12 ;
			reg					pci_ba5_bit0 ;
			reg		[31 : 12]	pci_am5 ;
			reg		[31 : 12]	pci_ta5 ;
`endif
			reg		[31 : 24]	pci_err_cs_bit31_24 ;
			reg					pci_err_cs_bit10 ;
			reg					pci_err_cs_bit8 ;
			reg					pci_err_cs_bit0 ;
			reg		[31 : 0]	pci_err_addr ;
			reg		[31 : 0]	pci_err_data ;
                                
                                
/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
WISHBONE Slave configuration registers
	There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to 
	sign which bit or range of bits are implemented. Some special cases and examples are described below!
-------------------------------------------------------------------------------------------------------------
###########################################################################################################*/
                                
/*-----------------------------------------------------------------------------------------------------------
[800h-85Ch]                     
	Depending on defines (WB_IMAGE1 or .. or WB_IMAGE4 or WB_IMAGE5) in constants.v file, there are 
	registers corresponding to each IMAGE defined to REG and parameter wb_image_X assigned to '1'. 
	The maximum number of images is "6". By default there are first two images used and the first (WB_IMAGE0) 
	is assigned to Configuration space! With a 'define' WB_IMAGEx you choose the number of used WB IMAGES in 
	a bridge without WB_IMAGE0 (e.g. WB_IMAGE3 tells, that WB_IMAGE1, WB_IMAGE2 and WB_IMAGE3 are used for 
	mapping the space from PCI to WB. Offcourse, WB_IMAGE0 is assigned to Configuration space). That leave 
	us WB_IMAGE5 as the maximum number of images.                                             
          
	When error occurs, WISHBONE ERR_ADDR and ERR_DATA registers stores address and data on the bus that
	caused error. While ERR_CS register stores Byte Enables and Bus Command in the MSByte. In bits 10, 9
	and 8 it reports Retry Counter Expired (for posted writes), Error Source (Master Abort) and Error
	Report Signal (signals that error has occured) respectively. With bit 0 we enable Error Reporting 
	mechanism.                  
-----------------------------------------------------------------------------------------------------------*/
// WB_IMAGE0 is always assigned to config. space
			parameter			wb_image0 = 1 ; 
			wire	[2 : 0]		wb_img_ctrl0_bit2_0 = 3'b000 ; // NO addr.transl., pre-fetch and read-line 
			wire	[31 : 12]	wb_ba0_bit31_12 = `WB_CONFIGURATION_BASE ;
			wire				wb_ba0_bit0 = 0 ; // config. space is MEMORY space                 
			wire	[31 : 12]	wb_am0 = 20'hffff_f ; // 4KBytes of configuration space            
			wire	[31 : 12]	wb_ta0 = 20'h0000_0 ; // NO address translation needed             
// WB_IMAGE0 and WB_IMAGE1 are included by default meanwhile others are optional !
			parameter			wb_image1 = 1 ;
			reg		[2 : 0]		wb_img_ctrl1_bit2_0 ;
			reg		[31 : 12]	wb_ba1_bit31_12 ;
			reg					wb_ba1_bit0 ;
			reg		[31 : 12]	wb_am1 ;
			reg		[31 : 12]	wb_ta1 ;
`ifdef		WB_IMAGE2           
			parameter			wb_image2 = 1 ; 
			reg		[2 : 0]		wb_img_ctrl2_bit2_0 ;
			reg		[31 : 12]	wb_ba2_bit31_12 ;
			reg					wb_ba2_bit0 ;
			reg		[31 : 12]	wb_am2 ;
			reg		[31 : 12]	wb_ta2 ;

 			parameter			wb_image3 = 0 ;
            wire	[2 : 0]		wb_img_ctrl3_bit2_0 = 3'b000 ;
			wire	[31 : 12]	wb_ba3_bit31_12 = 20'h0000_0 ;    
            wire				wb_ba3_bit0 = 1'b0 ;        
            wire	[31 : 12]	wb_am3 = 20'h0000_0 ;             
            wire	[31 : 12]	wb_ta3 = 20'h0000_0 ;             

  			parameter			wb_image4 = 0 ;
            wire	[2 : 0]		wb_img_ctrl4_bit2_0 = 3'b000 ;
			wire	[31 : 12]	wb_ba4_bit31_12 = 20'h0000_0 ;    
            wire				wb_ba4_bit0 = 1'b0 ;        
            wire	[31 : 12]	wb_am4 = 20'h0000_0 ;             
            wire	[31 : 12]	wb_ta4 = 20'h0000_0 ;             

			parameter			wb_image5 = 0 ;
            wire	[2 : 0]		wb_img_ctrl5_bit2_0 = 3'b000 ;
			wire	[31 : 12]	wb_ba5_bit31_12 = 20'h0000_0 ;    
            wire				wb_ba5_bit0 = 1'b0 ;        
            wire	[31 : 12]	wb_am5 = 20'h0000_0 ;             
            wire	[31 : 12]	wb_ta5 = 20'h0000_0 ;             
`endif                        
`ifdef		WB_IMAGE3           
			parameter			wb_image2 = 1 ; 
			reg		[2 : 0]		wb_img_ctrl2_bit2_0 ;
			reg		[31 : 12]	wb_ba2_bit31_12 ;
			reg					wb_ba2_bit0 ;
			reg		[31 : 12]	wb_am2 ;
			reg		[31 : 12]	wb_ta2 ;

			parameter			wb_image3 = 1 ; 
			reg		[2 : 0]		wb_img_ctrl3_bit2_0 ;
			reg		[31 : 12]	wb_ba3_bit31_12 ;
			reg					wb_ba3_bit0 ;
			reg		[31 : 12]	wb_am3 ;
			reg		[31 : 12]	wb_ta3 ;

  			parameter			wb_image4 = 0 ;
            wire	[2 : 0]		wb_img_ctrl4_bit2_0 = 3'b000 ;
			wire	[31 : 12]	wb_ba4_bit31_12 = 20'h0000_0 ;    
            wire				wb_ba4_bit0 = 1'b0 ;        
            wire	[31 : 12]	wb_am4 = 20'h0000_0 ;             
            wire	[31 : 12]	wb_ta4 = 20'h0000_0 ;             

			parameter			wb_image5 = 0 ;
            wire	[2 : 0]		wb_img_ctrl5_bit2_0 = 3'b000 ;
			wire	[31 : 12]	wb_ba5_bit31_12 = 20'h0000_0 ;    
            wire				wb_ba5_bit0 = 1'b0 ;        
            wire	[31 : 12]	wb_am5 = 20'h0000_0 ;             
            wire	[31 : 12]	wb_ta5 = 20'h0000_0 ;             
`endif                        
`ifdef		WB_IMAGE4           
			parameter			wb_image2 = 1 ; 
			reg		[2 : 0]		wb_img_ctrl2_bit2_0 ;
			reg		[31 : 12]	wb_ba2_bit31_12 ;
			reg					wb_ba2_bit0 ;
			reg		[31 : 12]	wb_am2 ;
			reg		[31 : 12]	wb_ta2 ;

			parameter			wb_image3 = 1 ; 
			reg		[2 : 0]		wb_img_ctrl3_bit2_0 ;
			reg		[31 : 12]	wb_ba3_bit31_12 ;
			reg					wb_ba3_bit0 ;
			reg		[31 : 12]	wb_am3 ;
			reg		[31 : 12]	wb_ta3 ;

			parameter			wb_image4 = 1 ; 
			reg		[2 : 0]		wb_img_ctrl4_bit2_0 ;
			reg		[31 : 12]	wb_ba4_bit31_12 ;
			reg					wb_ba4_bit0 ;
			reg		[31 : 12]	wb_am4 ;
			reg		[31 : 12]	wb_ta4 ;

			parameter			wb_image5 = 0 ;
            wire	[2 : 0]		wb_img_ctrl5_bit2_0 = 3'b000 ;
			wire	[31 : 12]	wb_ba5_bit31_12 = 20'haa00_0 ;    //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
            wire				wb_ba5_bit0 = 1'b0 ;        
            wire	[31 : 12]	wb_am5 = 20'h0000_0 ;             
            wire	[31 : 12]	wb_ta5 = 20'h0000_0 ;             
`endif                        
`ifdef		WB_IMAGE5           
			parameter			wb_image2 = 1 ; 
			reg		[2 : 0]		wb_img_ctrl2_bit2_0 ;
			reg		[31 : 12]	wb_ba2_bit31_12 ;
			reg					wb_ba2_bit0 ;
			reg		[31 : 12]	wb_am2 ;
			reg		[31 : 12]	wb_ta2 ;

			parameter			wb_image3 = 1 ; 
			reg		[2 : 0]		wb_img_ctrl3_bit2_0 ;
			reg		[31 : 12]	wb_ba3_bit31_12 ;
			reg					wb_ba3_bit0 ;
			reg		[31 : 12]	wb_am3 ;
			reg		[31 : 12]	wb_ta3 ;