conf_space.v

PCI IP核功能实现

// GENERAL input to interrupt status register       
input							isr_int_prop ;      
input                           isr_err_int ;       
input                           isr_par_err_int ;   
input                           isr_sys_err_int ;   


/*###########################################################################################################
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
	REGISTERS definition
	====================
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
###########################################################################################################*/


/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
PCI CONFIGURATION SPACE HEADER (type 00h) registers

	BIST and some other registers are not implemented and therefor written in correct
	place with comment line. There are also some registers with NOT all bits implemented and therefor uses
	_bitX or _bitX2_X1 to sign which bit or range of bits are implemented. 
	Some special cases and examples are described below!
-------------------------------------------------------------------------------------------------------------
###########################################################################################################*/

/*-----------------------------------------------------------------------------------------------------------
[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
			r_ prefix is a sign for read only registers
	Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g. 
	Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
	together by application. Class_Code has 3 bytes to define BASE class (06h for PCI Bridge), SUB class 
	(00h for HOST type, 80h for Other Bridge type) and Interface type (00h for normal).
-----------------------------------------------------------------------------------------------------------*/
			parameter			r_vendor_id = `HEADER_VENDOR_ID ;	// 16'h2321 = 16'd8993 !!!
			parameter			r_device_id = `HEADER_DEVICE_ID ;
			reg					command_bit8 ;			
			reg					command_bit6 ;			
			reg		[2 : 0]		command_bit2_0 ;		
			reg		[15 : 11]	status_bit15_11 ;		
			parameter			r_status_bit10_9 = 2'b01 ;	// 2'b01 means MEDIUM devsel timing !!!
			reg					status_bit8 ;
			parameter			r_status_bit5 = `HEADER_66MHz ;   	// 1'b0 indicates 33 MHz capable !!!
			parameter			r_revision_id = `HEADER_REVISION_ID ;
`ifdef		HOST
			parameter			r_class_code = 24'h06_00_00 ;
`else
			parameter			r_class_code = 24'h06_80_00 ;
`endif
			reg		[7 : 0]		cache_line_size_reg	;
			reg		[7 : 0]		latency_timer ;
			parameter			r_header_type = 8'h00 ;
			// REG				bist							NOT implemented !!!

/*-----------------------------------------------------------------------------------------------------------
[010h-03Ch] all other DWORDs (32-bit) of PCI configuration header - only for HEADER type 00h !
			r_ prefix is a sign for read only registers
	BASE_ADDRESS_REGISTERS are the same as ones in the PCI Target configuration registers section. They
	are duplicated and therefor defined just ones and used with the same name as written below. If 
	IMAGEx is NOT defined there is only parameter image_X assigned to '0' and this parameter is used 
	elsewhere in the code. This parameter is defined in the INTERNAL SIGNALS part !!!
	Interrupt_Pin value 8'h01 is used for INT_A pin used.
	MIN_GNT and MAX_LAT are used for device's desired values for Latency Timer value. The value in boath
	registers specifies a period of time in units of 1/4 microsecond. ZERO indicates that there are no
	major requirements for the settings of Latency Timer. 
	MIN_GNT specifieshow how long a burst period the device needs at 33MHz. MAX_LAT specifies how often
	the device needs to gain access to the PCI bus. Values are choosen assuming that the target does not
	insert any wait states. Follow the expamle of settings for simple display card.
	If we use 64 (32-bit) FIFO locations for one burst then we need 8 x 1/4 microsecond periods at 33MHz
	clock rate => MIN_GNT = 08h ! Resolution is 1024 x 768 (= 786432 pixels for one frame) with 16-bit 
	color mode. We can transfere 2 16-bit pixels in one FIFO location. From that we calculate, that for
	one frame we need 6144 burst transferes in 1/25 second. So we need one burst every 6,51 microsecond
	and that is 26 x 1/4 microsecond or 1Ah x 1/4 microsecond => MAX_LAT = 1Ah !
-----------------------------------------------------------------------------------------------------------*/
			// REG x 6		base_address_register_X			IMPLEMENTED as		pci_ba_X !!!
			// REG			r_cardbus_cis_pointer			NOT implemented !!!
			// REG			r_subsystem_vendor_id			NOT implemented !!!
			// REG			r_subsystem_id					NOT implemented !!!
			// REG			r_expansion_rom_base_address	NOT implemented !!!
			// REG			r_cap_list_pointer				NOT implemented !!!
			reg		[7 : 0]	interrupt_line ;
			parameter		r_interrupt_pin = 8'h01 ;
			parameter		r_min_gnt = 8'h08 ;
			parameter		r_max_lat = 8'h1a ;


/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
PCI Bridge default image SIZE parameters
	This parameters are not part of any register group, but are needed for default image size configuration
	used in PCI Target and WISHBONE Slave configuration registers!
-------------------------------------------------------------------------------------------------------------
###########################################################################################################*/

/*-----------------------------------------------------------------------------------------------------------
	PCI Target default image size parameters are defined with masked bits for address mask registers of 
	each image space. By default there are 1MByte of address space defined for def_pci_imageX_addr_map 
	parameters!
-----------------------------------------------------------------------------------------------------------*/
			parameter		def_pci_image0_addr_map = 20'hfff0_0 ;
			parameter		def_pci_image1_addr_map = 20'hfff0_0 ;
			parameter		def_pci_image2_addr_map = 20'hfff0_0 ;
			parameter		def_pci_image3_addr_map = 20'hfff0_0 ;
			parameter		def_pci_image4_addr_map = 20'hfff0_0 ;
			parameter		def_pci_image5_addr_map = 20'hfff0_0 ;

/*-----------------------------------------------------------------------------------------------------------
	WISHBONE Slave default image size parameters are defined with masked bits for address mask registers 
	of each image space. By default there are 1MByte of address space defined for def_wb_imageX_addr_map 
	parameters except for def_wb_image0_addr_map which is used for configuration space!
-----------------------------------------------------------------------------------------------------------*/
			// PARAMETER	def_wb_image0_addr_map	IMPLEMENTED as r_wb_am0 parameter for CONF. space !!!
			parameter		def_wb_image1_addr_map = 20'hfff0_0 ;
			parameter		def_wb_image2_addr_map = 20'hfff0_0 ;
			parameter		def_wb_image3_addr_map = 20'hfff0_0 ;
			parameter		def_wb_image4_addr_map = 20'hfff0_0 ;
			parameter		def_wb_image5_addr_map = 20'hfff0_0 ;


/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
PCI Target configuration registers
	There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to 
	sign which bit or range of bits are implemented. Some special cases and examples are described below!
-------------------------------------------------------------------------------------------------------------
###########################################################################################################*/

/*-----------------------------------------------------------------------------------------------------------
[100h-168h] 
	Depending on defines (PCI_IMAGE1 or .. or PCI_IMAGE5 or (PCI_IMAGE6 and HOST)) in constants.v file, 
	there are registers corresponding to each IMAGE defined to REG and parameter pci_image_X assigned to '1'. 
	The maximum number of images is "6". By default there are first two images used and the first (PCI_IMAGE0) 
	is assigned to Configuration space! With a 'define' PCI_IMAGEx you choose the number of used PCI IMAGES 
	in a bridge without PCI_IMAGE0 (e.g. PCI_IMAGE3 tells, that PCI_IMAGE1, PCI_IMAGE2 and PCI_IMAGE3 are 
	used for mapping the space from WB to PCI. Offcourse, PCI_IMAGE0 is assigned to Configuration space). 
	That leave us PCI_IMAGE5 as the maximum number of images.
	There is one exeption, when the core is implemented as HOST. If so, then the PCI specification allowes 
	the Configuration space NOT to be visible on the PCI bus. With `define PCI_IMAGE6 (and `define HOST), we 
	assign PCI_IMAGE0 to normal WB to PCI image and not to configuration space!                   

	When error occurs, PCI ERR_ADDR and ERR_DATA registers stores address and data on the bus that
	caused error. While ERR_CS register stores Byte Enables and Bus Command in the MSByte. In bits 10
	and 8 it reports Retry Counter Expired (for posted writes), Error Source (Master Abort) and Error
	Report Signal (signals that error has occured) respectively. With bit 0 we enable Error Reporting 
	mechanism.
-----------------------------------------------------------------------------------------------------------*/
			parameter			pci_image0 = 1 ;
			reg		[31 : 12]	pci_ba0_bit31_12 ;
`ifdef		HOST
	`ifdef	PCI_IMAGE6	// if PCI bridge is HOST and IMAGE0 is assigned as general image space
			parameter			pci_image0_conf = 1 ;
			reg		[2 : 1]		pci_img_ctrl0_bit2_1 ;
			reg					pci_ba0_bit0 ;
			reg		[31 : 12]	pci_am0 ;
			reg		[31 : 12]	pci_ta0 ;
	`else // if PCI bridge is HOST and IMAGE0 is assigned to PCI configuration space
			parameter			pci_image0_conf = 0 ;
			wire	[2 : 1]		pci_img_ctrl0_bit2_1 = 2'b00 ; // NO pre-fetch and read line support
			wire				pci_ba0_bit0 = 0 ; // config. space is MEMORY space
			wire	[31 : 12]	pci_am0 = 20'hffff_f ; // 4KBytes of configuration space
			wire	[31 : 12]	pci_ta0 = 20'h0000_0 ; // NO address translation needed
	`endif
`else // if PCI bridge is GUEST, then IMAGE0 is assigned to PCI configuration space
			parameter			pci_image0_conf = 0 ;
			wire	[2 : 1]		pci_img_ctrl0_bit2_1 = 2'b00 ; // NO addr.transl. and pre-fetch
			wire				pci_ba0_bit0 = 0 ; // config. space is MEMORY space
			wire	[31 : 12]	pci_am0 = 20'hffff_f ; // 4KBytes of configuration space
			wire	[31 : 12]	pci_ta0 = 20'h0000_0 ; // NO address translation needed
`endif
			parameter			pci_image1 = 1 ;
			reg		[2 : 1]		pci_img_ctrl1_bit2_1 ;
			reg		[31 : 12]	pci_ba1_bit31_12 ;
			reg					pci_ba1_bit0 ;
			reg		[31 : 12]	pci_am1 ;
			reg		[31 : 12]	pci_ta1 ;

// IMAGE0 and IMAGE1 are included by default, meanwhile other IMAGEs are optional !!!
`ifdef		PCI_IMAGE2              
			parameter			pci_image2 = 1 ;
			reg		[2 : 1]		pci_img_ctrl2_bit2_1 ;
			reg		[31 : 12]	pci_ba2_bit31_12 ;
			reg					pci_ba2_bit0 ;
			reg		[31 : 12]	pci_am2 ;
			reg		[31 : 12]	pci_ta2 ;

 			parameter			pci_image3 = 0 ;
            wire	[2 : 1]		pci_img_ctrl3_bit2_1 = 2'b00 ;
			wire	[31 : 12]	pci_ba3_bit31_12 = 20'h0000_0 ;    
            wire				pci_ba3_bit0 = 1'b0 ;        
            wire	[31 : 12]	pci_am3 = 20'h0000_0 ;             
            wire	[31 : 12]	pci_ta3 = 20'h0000_0 ;             

  			parameter			pci_image4 = 0 ;
            wire	[2 : 1]		pci_img_ctrl4_bit2_1 = 2'b00 ;
			wire	[31 : 12]	pci_ba4_bit31_12 = 20'h0000_0 ;    
            wire				pci_ba4_bit0 = 1'b0 ;        
            wire	[31 : 12]	pci_am4 = 20'h0000_0 ;             
            wire	[31 : 12]	pci_ta4 = 20'h0000_0 ;             

			parameter			pci_image5 = 0 ;
            wire	[2 : 1]		pci_img_ctrl5_bit2_1 = 2'b00 ;
			wire	[31 : 12]	pci_ba5_bit31_12 = 20'h0000_0 ;    
            wire				pci_ba5_bit0 = 1'b0 ;        
            wire	[31 : 12]	pci_am5 = 20'h0000_0 ;             
            wire	[31 : 12]	pci_ta5 = 20'h0000_0 ;             
`endif
`ifdef		PCI_IMAGE3              
			parameter			pci_image2 = 1 ;
			reg		[2 : 1]		pci_img_ctrl2_bit2_1 ;
			reg		[31 : 12]	pci_ba2_bit31_12 ;
			reg					pci_ba2_bit0 ;
			reg		[31 : 12]	pci_am2 ;
			reg		[31 : 12]	pci_ta2 ;

			parameter			pci_image3 = 1 ;
			reg		[2 : 1]		pci_img_ctrl3_bit2_1 ;
			reg		[31 : 12]	pci_ba3_bit31_12 ;
			reg					pci_ba3_bit0 ;
			reg		[31 : 12]	pci_am3 ;
			reg		[31 : 12]	pci_ta3 ;

  			parameter			pci_image4 = 0 ;
            wire	[2 : 1]		pci_img_ctrl4_bit2_1 = 2'b00 ;
			wire	[31 : 12]	pci_ba4_bit31_12 = 20'h0000_0 ;    
            wire				pci_ba4_bit0 = 1'b0 ;        
            wire	[31 : 12]	pci_am4 = 20'h0000_0 ;             
            wire	[31 : 12]	pci_ta4 = 20'h0000_0 ;             

			parameter			pci_image5 = 0 ;
            wire	[2 : 1]		pci_img_ctrl5_bit2_1 = 2'b00 ;
			wire	[31 : 12]	pci_ba5_bit31_12 = 20'h0000_0 ;    
            wire				pci_ba5_bit0 = 1'b0 ;        
            wire	[31 : 12]	pci_am5 = 20'h0000_0 ;             
            wire	[31 : 12]	pci_ta5 = 20'h0000_0 ;             
`endif