conf_space.v

PCI IP核功能实现

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name: conf_space.v                                     ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - [e-mail]                                   ////
////      - Tadej Markovic                                        ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Tadej Markovic, [e-mail]       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: conf_space.v,v $
// Revision 1.2  2001/07/19 09:52:35  mihad
// Only delayed write storage is provided after merging delayed requests.
// All delayed reads now pass through FIFO.
//
//

`include "constants.v"

/*-----------------------------------------------------------------------------------------------------------
	w_ prefix is a sign for Write (and read) side of Dual-Port registers
	r_ prefix is a sign for Read only side of Dual-Port registers
In the first line there are DATA and ADDRESS ports, in the second line there are write enable and read 
enable signals with chip-select (conf_hit) for config. space.
In the third line there are output signlas from Command register of the PCI configuration header !!!
In the fourth line there are input signals to Status register of the PCI configuration header !!!
In the fifth line there is output from Latency Timer & r_Interrupt pin registers of the PCI conf. header !!!
Following are IMAGE specific registers, from which PCI_BASE_ADDR registers are the same as base address
registers from the PCI conf. header !!!
-----------------------------------------------------------------------------------------------------------*/
					// normal R/W address, data and control
module CONF_SPACE (	w_conf_address_in, w_conf_data_in, w_conf_data_out, r_conf_address_in, r_conf_data_out, 
					w_we, w_re, r_re, w_byte_en, conf_hit, w_clock, reset, pci_clk, wb_clk,
					// outputs from command register of the PCI header
					serr_enable, perr_response, pci_master_enable, memory_space_enable, io_space_enable,
					// inputs to status register of the PCI header
					perr_in, serr_in, master_abort_recv, target_abort_recv, target_abort_set, master_data_par_err,
					// output from cache_line_size, latency timer and r_interrupt_pin register of the PCI header
					cache_line_size, latency_tim, int_pin,
					// output from all pci IMAGE registers
					pci_base_addr0, pci_base_addr1, pci_base_addr2, pci_base_addr3, pci_base_addr4, pci_base_addr5, 
					pci_memory_io0, pci_memory_io1, pci_memory_io2, pci_memory_io3, pci_memory_io4, pci_memory_io5, 
					pci_addr_mask0, pci_addr_mask1, pci_addr_mask2, pci_addr_mask3, pci_addr_mask4, pci_addr_mask5, 
					pci_tran_addr0, pci_tran_addr1, pci_tran_addr2, pci_tran_addr3, pci_tran_addr4, pci_tran_addr5, 
					pci_img_ctrl0,  pci_img_ctrl1,  pci_img_ctrl2,  pci_img_ctrl3,  pci_img_ctrl4,  pci_img_ctrl5,
					// input to pci error control and status register, error address and error data registers
					pci_error_be, pci_error_bc, pci_error_rty_exp, pci_error_sig, pci_error_addr, pci_error_data,
					// output from pci error control and status register
					pci_error_en, pci_error_sig_set, pci_error_rty_exp_set, 
					// output from all wishbone IMAGE registers                                                                                          
					wb_base_addr0, wb_base_addr1, wb_base_addr2, wb_base_addr3, wb_base_addr4, wb_base_addr5,
					wb_memory_io0, wb_memory_io1, wb_memory_io2, wb_memory_io3, wb_memory_io4, wb_memory_io5, 
					wb_addr_mask0, wb_addr_mask1, wb_addr_mask2, wb_addr_mask3, wb_addr_mask4, wb_addr_mask5,
					wb_tran_addr0, wb_tran_addr1, wb_tran_addr2, wb_tran_addr3, wb_tran_addr4, wb_tran_addr5,
					wb_img_ctrl0,  wb_img_ctrl1,  wb_img_ctrl2,  wb_img_ctrl3,  wb_img_ctrl4,  wb_img_ctrl5, 
					// input to wb error control and status register, error address and error data registers
					wb_error_be, wb_error_bc, wb_error_rty_exp, wb_error_es, wb_error_sig, wb_error_addr, wb_error_data,
					// output from wb error control and status register
					wb_error_en, wb_error_sig_set, wb_error_rty_exp_set, 
					// output from conf. cycle generation register (sddress) & int. control register
					config_addr, icr_soft_res, serr_int_en, perr_int_en, error_int_en, int_prop_en,
					// input to interrupt status register
					isr_int_prop, isr_err_int, isr_par_err_int, isr_sys_err_int	) ;
                    
                    
/*###########################################################################################################
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
	Input and output ports
	======================
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
###########################################################################################################*/

// output data 
output	[31 : 0]				w_conf_data_out ;
output	[31 : 0]				r_conf_data_out ;
reg		[31 : 0]				w_conf_data_out ;
reg		[31 : 0]				r_conf_data_out ;
// input data
input	[31 : 0]				w_conf_data_in ;
// input address
input	[11 : 0]				w_conf_address_in ;
input	[11 : 0]				r_conf_address_in ;
// input control signals
input							w_we ;
input							w_re ;
input							r_re ;
input	[3 : 0]					w_byte_en ;
input							conf_hit ;
input							w_clock ;
input							reset ;
input							pci_clk ;
input							wb_clk ;
// PCI header outputs from command register
output							serr_enable ;
output							perr_response ;
output							pci_master_enable ;
output							memory_space_enable ;
output							io_space_enable ;
// PCI header inputs to status register
input							perr_in ;
input							serr_in ;
input							master_abort_recv ;
input							target_abort_recv ;
input							target_abort_set ;
input							master_data_par_err ;
// PCI header output from cache_line_size, latency timer and interrupt pin
output	[7 : 0]					cache_line_size ;
output	[7 : 0]					latency_tim ;
output	[2 : 0]					int_pin ; // only 3 LSbits are important!
// PCI output from image registers
output	[31 : 12]				pci_base_addr0 ; 
output  [31 : 12]               pci_base_addr1 ; 
output  [31 : 12]               pci_base_addr2 ; 
output  [31 : 12]               pci_base_addr3 ; 
output  [31 : 12]               pci_base_addr4 ; 
output  [31 : 12]               pci_base_addr5 ; 
output							pci_memory_io0 ;
output							pci_memory_io1 ;
output							pci_memory_io2 ;
output							pci_memory_io3 ;
output							pci_memory_io4 ;
output							pci_memory_io5 ;
output  [31 : 12]               pci_addr_mask0 ; 
output  [31 : 12]               pci_addr_mask1 ; 
output  [31 : 12]               pci_addr_mask2 ; 
output  [31 : 12]               pci_addr_mask3 ; 
output  [31 : 12]               pci_addr_mask4 ; 
output  [31 : 12]               pci_addr_mask5 ; 
output  [31 : 12]               pci_tran_addr0 ; 
output  [31 : 12]               pci_tran_addr1 ; 
output  [31 : 12]               pci_tran_addr2 ; 
output  [31 : 12]               pci_tran_addr3 ; 
output  [31 : 12]               pci_tran_addr4 ; 
output  [31 : 12]               pci_tran_addr5 ; 
output  [2 : 1]                 pci_img_ctrl0 ;  
output  [2 : 1]                 pci_img_ctrl1 ;  
output  [2 : 1]                 pci_img_ctrl2 ;  
output  [2 : 1]                 pci_img_ctrl3 ;  
output  [2 : 1]                 pci_img_ctrl4 ;  
output  [2 : 1]                 pci_img_ctrl5 ;  
// PCI input to pci error control and status register, error address and error data registers
input	[3 : 0]					pci_error_be ;     
input   [3 : 0]                 pci_error_bc ;     
input                           pci_error_rty_exp ;
input                           pci_error_sig ;    
input   [31 : 0]                pci_error_addr ;   
input   [31 : 0]                pci_error_data ;    
// PCI output from pci error control and status register
output							pci_error_en ; 
output							pci_error_sig_set ;
output							pci_error_rty_exp_set ;
// WISHBONE output from image registers
output	[31 : 12]   			wb_base_addr0 ;
output  [31 : 12]               wb_base_addr1 ;
output  [31 : 12]               wb_base_addr2 ;
output  [31 : 12]               wb_base_addr3 ;
output  [31 : 12]               wb_base_addr4 ;
output  [31 : 12]               wb_base_addr5 ;
output							wb_memory_io0 ;
output							wb_memory_io1 ;
output							wb_memory_io2 ;
output							wb_memory_io3 ;
output							wb_memory_io4 ;
output							wb_memory_io5 ;
output  [31 : 12]               wb_addr_mask0 ;
output  [31 : 12]               wb_addr_mask1 ;
output  [31 : 12]               wb_addr_mask2 ;
output  [31 : 12]               wb_addr_mask3 ;
output  [31 : 12]               wb_addr_mask4 ;
output  [31 : 12]               wb_addr_mask5 ;
output  [31 : 12]               wb_tran_addr0 ;
output  [31 : 12]               wb_tran_addr1 ;
output  [31 : 12]               wb_tran_addr2 ;
output  [31 : 12]               wb_tran_addr3 ;
output  [31 : 12]               wb_tran_addr4 ;
output  [31 : 12]               wb_tran_addr5 ;
output  [2 : 0]                 wb_img_ctrl0 ; 
output  [2 : 0]                 wb_img_ctrl1 ; 
output  [2 : 0]                 wb_img_ctrl2 ; 
output  [2 : 0]                 wb_img_ctrl3 ; 
output  [2 : 0]                 wb_img_ctrl4 ; 
output  [2 : 0]                 wb_img_ctrl5 ; 
// WISHBONE input to wb error control and status register, error address and error data registers
input	[3 : 0] 				wb_error_be ;     
input   [3 : 0]	                wb_error_bc ;     
input   		                wb_error_rty_exp ;
input                           wb_error_es ;     
input                           wb_error_sig ;    
input   [31 : 0]                wb_error_addr ;   
input   [31 : 0]                wb_error_data ;   
// WISHBONE output from wb error control and status register
output							wb_error_en ; 
output							wb_error_sig_set ;
output							wb_error_rty_exp_set ;
// GENERAL output from conf. cycle generation register & int. control register 
output	[23 : 0]				config_addr ; 		
output                          icr_soft_res ;
output                          serr_int_en ;
output                          perr_int_en ;
output                          error_int_en ;
output                          int_prop_en ;