grey_to_norm.vhd

来自「异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity grey_to_norm is
    generic(width:integer:=8);
    port(din:in std_logic_vector(width-1 downto 0);
         dout:out std_logic_vector(width-1 downto 0)
         );
end entity;

architecture rtl of grey_to_norm is
  begin
  process(din)
  variable tempd:std_logic;
    begin
         for i in width-1 downto 0 loop 
             tempd:='0';
             for j in width-1 downto i loop 
                 tempd:=tempd xor din(j);
             end loop;
             dout(i)<=tempd;
         end loop;
   end process;
end architecture;