rd_sector.vhd

异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rd_sector is
  generic(width:integer:=8);
  port(rd_clk,rden,clr,rd_add_co:in std_logic;
       rd_add:in std_logic_vector(width-1 downto 0); 
       rd_wr_add_grey:std_logic_vector(width downto 0); 
       rd_add_grey:out std_logic_vector(width downto 0);
       empty,al_empty:out std_logic             
       );
end entity;

architecture rtl of rd_sector is
   
   signal radd,raddp,radd_grey,radd_grey_temp,rd_wadd_grey,rd_wr_grey,
          rd_wadd_temp,rd_wadd,wadd_grey:std_logic_vector(width-1 downto 0);
   signal rd_wr_add_greyp:std_logic_vector(width downto 0); 
   signal radd_co,rd_wr_add_co:std_logic;

   component norm_to_grey 
       port(din:in std_logic_vector(width-1 downto 0);
            dout:out std_logic_vector(width-1 downto 0)
           );
   end component;

   component grey_to_norm
        port(din:in std_logic_vector(width-1 downto 0);
             dout:out std_logic_vector(width-1 downto 0)
            );
   end component;

   component dffx
       port(din:in std_logic_vector(width-1 downto 0);
            clk:in std_logic;
            dout:out std_logic_vector(width-1 downto 0));
   end component;
   
begin 

--读地址产生模块，此程序同时产生读地址的自然码和格雷码：radd,radd_grey,radd_co
        
       -- rd_addr_out<=radd; 
       -- raddp<=radd+1; 
        
        raddp<=rd_add;
        rd_add_grey<=radd_co&radd_grey;
        u1:norm_to_grey port map(raddp,radd_grey_temp);
        wadd_process:process(clr,rd_clk)
            begin
                if clr='1' then
                   radd<=(others=>'0');
                   radd_grey<=(others=>'0');
                   radd_co<='0';
                elsif rd_clk'event and rd_clk='1' then
                    if rden='1' then
                       radd<=raddp;
                       radd_grey<=radd_grey_temp;
                       radd_co<=rd_add_co;
                    end if;
                end if;
         end process;

--获取读时钟采样的自然码和格雷码的写地址以及进位标志:rd_wadd,rd_wadd_grey,rd_wadd_co
        u3:dffx port map(rd_wr_add_grey,rd_clk,rd_wr_add_greyp);
        --rd_wr_add_greyp<=rd_wr_add_grey;
        rd_wr_grey<=rd_wr_add_greyp(width-1 downto 0);
        rd_wr_add_co<=rd_wr_add_greyp(width);
        u2:grey_to_norm port map(rd_wr_grey,rd_wadd_temp);
        process(clr,rd_clk)
            begin
                if clr='1' then
                    rd_wadd_grey<=(others=>'0');
                    rd_wadd<=(Others=>'0');
                    rd_wadd_co<='0';
                elsif rd_clk'event and rd_clk='1' then
                    rd_wadd_grey<=rd_wr_add_greyp;-----
                    rd_wadd<=rd_wadd_temp;
                    rd_wadd_co<=rd_wr_add_co;
                end if;
        end process;

--空标志产生模块
        --rd_compare<=radd-rd_wadd;
       empty_process:process(clr,rd_clk)
           begin
               if clr='1' then
                   empty<='1';
               elsif rd_clk'event and rd_clk='1'  then
                  -- if(rden='1') then
                       if((rd_wadd-radd=1)and(radd_co/=rd_wadd_co)) or
                         (rd_wadd="00000000"and radd="11111111") then 
                           empty<='1';
                       else 
                           empty<='0';
                       end if;
                   
                  
               end if;
       end process;
-------------------------------------------------------------------
--将空标志产生模块
     almost_empty_process:process(clr,rd_clk)
       begin
             if(clr='0') then
                   al_empty<='0';
               elsif rd_clk'event and rd_clk='1' then
                  if(radd_co=rd_wadd_co) then
                       if ((radd>0 and radd<=246) and (rd_wadd-radd=9)) or
                           ((radd>246 and radd<=255) and  (radd-rd_wadd=247)) then 
                           al_empty<='1';
                       else 
                           al_empty<='0';
                       end if;
               end if;
           end if;
         
      end process;

---------------------------------------------------------------------------
end architecture;