dffx.vhd

来自「异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实」· VHDL 代码 · 共 19 行

library ieee;
use ieee.std_logic_1164.all;

entity dffx is
generic(width:integer:=8);
port(din:in std_logic_vector(width-1 downto 0);
     clk:in std_logic;
     dout:out std_logic_vector(width-1 downto 0));
end entity;

architecture behav of dffx is
    begin
    process(clk)
        begin 
            if(clk'event and clk='1') then
                dout<=din;
            end if;
    end process;
end architecture;