ram.vhd

异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ram is
    GENERIC(l:integer:=256;
            w:integer:=8);             
    port(wr_clk_ram,wren_ram,rd_clk_ram,rden_ram,
         full_ram,empty_ram,ha_full_ram,rst:in std_logic;
         datain:in std_logic_vector(w-1 downto 0);
         dataout,waddr_ram,raddr_ram:out std_logic_vector(w-1 downto 0);
         waddr_co,raddr_co:out std_logic
         ); 
end entity;

architecture behav of ram is
type memory is array(0 to l-1) of std_logic_vector(w-1 downto 0);
signal ram_ar:memory;
signal in_full,in_empty,ha_full_en,wp_co,rp_co:std_logic;
signal wp,rp:integer range 0 to l-1;
    begin
       in_full<=full_ram;
       in_empty<=empty_ram;
       waddr_ram<=conv_std_logic_vector(wp,w);
       raddr_ram<=conv_std_logic_vector(rp,w);
       --wp<=conv_integer(waddr_ram);
       --rp<=conv_integer(raddr_ram);    

--数据写堆栈       
    process(wr_clk_ram)
        begin
            if(wr_clk_ram'event and wr_clk_ram='1') then
                if(wren_ram='1' and in_full='0') then
                    ram_ar(wp)<=datain;
                end if;
            end if;
    end process;

--数据读堆栈
    process(rd_clk_ram)
        begin 
            if(rd_clk_ram'event and rd_clk_ram='1') then
                if(rden_ram='1' and in_empty='0')then
                dataout<=ram_ar(rp);
                end if;
            end if;
    end process;

--写指针wp的描述      
    waddr_co<=wp_co;             --写指针进位标志
    process(wr_clk_ram,rst)
        begin 
        if(rst='1') then
            wp<=0;wp_co<='0';
        elsif(wr_clk_ram'event and wr_clk_ram='1') then
            if(wren_ram='1' and in_full='0') then
                if(wp=l-1)then
                    wp<=0;
                    wp_co<=wp_co+'1';
                else
                    wp<=wp+1;
                end if;
            end if;
        end if;
    end process;

--读指针rp的描述             
    raddr_co<=rd_co;             --读指针进位标志
    process(rd_clk_ram,rst)
        begin
        if(rst='1') then
            rp<=0;
            rd_co<='0';
        elsif(rd_clk_ram'event and rd_clk_ram='1') then
            if(rden_ram='1' and in_empty='0') then
                if(ha_full_en='1') then
                
            

                  
                    if(rp=l-1)then
                        rp<=0;
                        rd_co<=rd_co+'1';
                    else
                        rp<=rp+1;
                    end if;
               end if;
            end if;
        end if;
    end process;

    process(ha_full_ram,wr_clk_ram)
        begin
            if(wr_clk_ram'event and wr_clk_ram='1')then
                if(ha_full_ram='1') then
                    ha_full_en<='1';
                elsif(in_empty='1') then
                    ha_full_en<='0';
                end if;   
             end if;
    end process; 

    






end architecture;