fifo.vhd

异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity fifo is
GENERIC(--l:integer:=256;
            w:integer:=8);  
port(wr_clk,rd_clk,rst:in std_logic;
     wr_en,rd_en:in std_logic;
     data_in:in std_logic_vector(w-1 downto 0); 
     data_out:out std_logic_vector(w-1 downto 0)
    );
end entity;

architecture rtl of fifo is
    signal i_full,i_empty,i_hafull,i_dataout:std_logic;
    signal i_waddr,i_raddr,p_dataout,i_wr_grey,i_rd_grey:std_logic_vector(w-1 downto 0);



    component ram
       -- GENERIC(w:integer:=8); 
         port(wr_clk_ram,wren_ram,rd_clk_ram,rden_ram,
              full_ram,empty_ram,ha_full_ram,rst:in std_logic;
              datain:in std_logic_vector(w-1 downto 0);
              dataout,waddr_ram,raddr_ram:out std_logic_vector(w-1 downto 0)
              );
    end component;

    component rd_sector
       generic(width:integer:=8);
        port(rd_clk,rden,clr:in std_logic;
             rd_add,rd_wr_add_grey:in std_logic_vector(width-1 downto 0); 
             rd_add_grey:out std_logic_vector(width-1 downto 0);
             empty:out std_logic             
             );
    end component;

    component wr_sector
        generic(width:integer:=8);
        port(wr_clk,wren,clr:in std_logic;
             wr_add:in std_logic_vector(width-1 downto 0);    
             wr_rd_add_grey:in std_logic_vector(width-1 downto 0);             
             wr_add_grey:out std_logic_vector(width-1 downto 0);
             full,ha_full:out std_logic
             ); 
    end component;


    begin
        ram1: ram
            port map(wr_clk_ram =>wr_clk,
                     wren_ram   =>wr_en,
                     rd_clk_ram =>rd_clk,
                     rden_ram   =>rd_en,
                     full_ram   =>i_full,
                     empty_ram  =>i_empty,
                     ha_full_ram=>i_hafull,
                     rst        =>rst,
                     datain     =>data_in,
                     dataout    =>p_dataout,
                     waddr_ram  =>i_waddr,
                     raddr_ram  =>i_raddr
                     
                     );  

        rd_sector1: rd_sector
            port map(rd_clk     =>rd_clk,
                     rden       =>rd_en,
                     clr        =>rst,
                     rd_add     =>i_raddr,
                     rd_wr_add_grey=>i_wr_grey,
                     rd_add_grey=>i_rd_grey,             
                     empty      =>i_empty
                     
                     );
      
        wr_sector1:wr_sector
            port map(wr_clk     =>wr_clk,
                     wren       =>wr_en,
                     clr        =>rst,
                     wr_add     =>i_waddr,
                     wr_rd_add_grey=>i_rd_grey,
                     wr_add_grey=>i_wr_grey,
                     ha_full    =>i_hafull,
                     full=>i_full
                     );

    
     data_out  <=p_dataout;
     
end architecture;