norm_to_grey.vhd

来自「异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实」· VHDL 代码 · 共 15 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity norm_to_grey is
    generic(width:integer:=8);
    port(din:in std_logic_vector(width-1 downto 0);
         dout:out std_logic_vector(width-1 downto 0)
         );
end entity;

architecture rtl of norm_to_grey is 
  begin
  dout<=din xor('0' & din(width-1 downto 1));
end architecture;