sditest.tan.qmsg

基于EP3C25的Altera SDI IP核的使用

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version " "Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 12 17:52:21 2008 " "Info: Processing started: Thu Jun 12 17:52:21 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off sditest -c sditest --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sditest -c sditest --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "sdiin sdiout 9.191 ns Longest " "Info: Longest tpd from source pin \"sdiin\" to destination pin \"sdiout\" is 9.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.798 ns) 0.798 ns sdiin 1 PIN PIN_D2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.798 ns) = 0.798 ns; Loc. = PIN_D2; Fanout = 1; PIN Node = 'sdiin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sdiin } "NODE_NAME" } } { "sditest.bdf" "" { Schematic "F:/vhdl_pro/sditest/sditest.bdf" { { 216 208 376 232 "sdiin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.668 ns) + CELL(2.725 ns) 9.191 ns sdiout 2 PIN PIN_C1 0 " "Info: 2: + IC(5.668 ns) + CELL(2.725 ns) = 9.191 ns; Loc. = PIN_C1; Fanout = 0; PIN Node = 'sdiout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.393 ns" { sdiin sdiout } "NODE_NAME" } } { "sditest.bdf" "" { Schematic "F:/vhdl_pro/sditest/sditest.bdf" { { 216 480 656 232 "sdiout" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.523 ns ( 38.33 % ) " "Info: Total cell delay = 3.523 ns ( 38.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.668 ns ( 61.67 % ) " "Info: Total interconnect delay = 5.668 ns ( 61.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.191 ns" { sdiin sdiout } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.191 ns" { sdiin {} sdiin~combout {} sdiout {} } { 0.000ns 0.000ns 5.668ns } { 0.000ns 0.798ns 2.725ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "116 " "Info: Allocated 116 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 12 17:52:23 2008 " "Info: Processing ended: Thu Jun 12 17:52:23 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}