prev_cmp_sditest.qmsg

基于EP3C25的Altera SDI IP核的使用

{ "Info" "ISTA_NO_PATHS_TO_REPORT" "setup " "Info: No setup paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "hold " "Info: No hold paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "recovery " "Info: No recovery paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "removal " "Info: No removal paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Warning" "WSTA_NO_ASSIGNMENTS_TO_REPORT" "report_min_pulse_width " "Warning: Command report_min_pulse_width could not find any constraints or exceptions to report" {  } {  } 0 0 "Command %1!s! could not find any constraints or exceptions to report" 0 0 "" 0}
{ "Info" "0" "" "Info: Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "" 0}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "Info: No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 0 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "" 0}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "Warning: No clocks defined in design." {  } {  } 0 0 "No clocks defined in design." 0 0 "" 0}
{ "Warning" "WSTA_NO_ASSIGNMENTS_TO_REPORT" "report_clock_fmax_summary " "Warning: Command report_clock_fmax_summary could not find any constraints or exceptions to report" {  } {  } 0 0 "Command %1!s! could not find any constraints or exceptions to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "setup " "Info: No setup paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "hold " "Info: No hold paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "recovery " "Info: No recovery paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "removal " "Info: No removal paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Warning" "WSTA_NO_ASSIGNMENTS_TO_REPORT" "report_min_pulse_width " "Warning: Command report_min_pulse_width could not find any constraints or exceptions to report" {  } {  } 0 0 "Command %1!s! could not find any constraints or exceptions to report" 0 0 "" 0}
{ "Info" "0" "" "Info: Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "" 0}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "Info: No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 0 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "" 0}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "Warning: No clocks defined in design." {  } {  } 0 0 "No clocks defined in design." 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "setup " "Info: No setup paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "hold " "Info: No hold paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "recovery " "Info: No recovery paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "removal " "Info: No removal paths to report" {  } {  } 0 0 "No %1!s! paths to report" 0 0 "" 0}
{ "Warning" "WSTA_NO_ASSIGNMENTS_TO_REPORT" "report_min_pulse_width " "Warning: Command report_min_pulse_width could not find any constraints or exceptions to report" {  } {  } 0 0 "Command %1!s! could not find any constraints or exceptions to report" 0 0 "" 0}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Info: Design is not fully constrained for setup requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Info: Design is not fully constrained for hold requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 10 s Quartus II " "Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "197 " "Info: Allocated 197 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 12 17:54:38 2008 " "Info: Processing ended: Thu Jun 12 17:54:38 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 18 s " "Info: Quartus II Full Compilation was successful. 0 errors, 18 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}