sditest.fit.rpt

基于EP3C25的Altera SDI IP核的使用

; Optimize Fast-Corner Timing                                           ; Off                                   ; Off                                   ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                                  ; Care                                  ;
; PowerPlay Power Optimization                                          ; Normal compilation                    ; Normal compilation                    ;
; Optimize Timing                                                       ; Normal compilation                    ; Normal compilation                    ;
; Optimize IOC Register Placement for Timing                            ; On                                    ; On                                    ;
; Limit to One Fitting Attempt                                          ; Off                                   ; Off                                   ;
; Final Placement Optimizations                                         ; Automatically                         ; Automatically                         ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                         ; Automatically                         ;
; Fitter Initial Placement Seed                                         ; 1                                     ; 1                                     ;
; PCI I/O                                                               ; Off                                   ; Off                                   ;
; Weak Pull-Up Resistor                                                 ; Off                                   ; Off                                   ;
; Enable Bus-Hold Circuitry                                             ; Off                                   ; Off                                   ;
; Auto Global Memory Control Signals                                    ; Off                                   ; Off                                   ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                                  ; Auto                                  ;
; Auto Delay Chains                                                     ; On                                    ; On                                    ;
; Allow Single-ended Buffer for Differential-XSTL Input                 ; Off                                   ; Off                                   ;
; Treat Bidirectional Pin as Output Pin                                 ; Off                                   ; Off                                   ;
; Auto Merge PLLs                                                       ; On                                    ; On                                    ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                                   ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                                   ; Off                                   ;
; Perform Register Duplication for Performance                          ; Off                                   ; Off                                   ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                                   ; Off                                   ;
; Perform Register Retiming for Performance                             ; Off                                   ; Off                                   ;
; Perform Asynchronous Signal Pipelining                                ; Off                                   ; Off                                   ;
; Physical Synthesis Effort Level                                       ; Normal                                ; Normal                                ;
; Logic Cell Insertion - Logic Duplication                              ; Auto                                  ; Auto                                  ;
; Auto Register Duplication                                             ; Auto                                  ; Auto                                  ;
; Auto Global Clock                                                     ; On                                    ; On                                    ;
; Auto Global Register Control Signals                                  ; On                                    ; On                                    ;
; Reserve all unused pins                                               ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
; Stop After Congestion Map Generation                                  ; Off                                   ; Off                                   ;
; Save Intermediate Fitting Results                                     ; Off                                   ; Off                                   ;
+-----------------------------------------------------------------------+---------------------------------------+---------------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/vhdl_pro/sditest/sditest.pin.


+-------------------------------------------------------------------+
; Fitter Resource Usage Summary                                     ;
+---------------------------------------------+---------------------+
; Resource                                    ; Usage               ;
+---------------------------------------------+---------------------+
; Total logic elements                        ; 0 / 24,624 ( 0 % )  ;
;     -- Combinational with no register       ; 0                   ;
;     -- Register only                        ; 0                   ;
;     -- Combinational with a register        ; 0                   ;
;                                             ;                     ;
; Logic element usage by number of LUT inputs ;                     ;
;     -- 4 input functions                    ; 0                   ;
;     -- 3 input functions                    ; 0                   ;
;     -- <=2 input functions                  ; 0                   ;
;     -- Register only                        ; 0                   ;
;                                             ;                     ;
; Logic elements by mode                      ;                     ;
;     -- normal mode                          ; 0                   ;
;     -- arithmetic mode                      ; 0                   ;
;                                             ;                     ;
; Total registers*                            ; 0 / 25,865 ( 0 % )  ;
;     -- Dedicated logic registers            ; 0 / 24,860 ( 0 % )  ;
;     -- I/O registers                        ; 0 / 1,005 ( 0 % )   ;
;                                             ;                     ;
; Total LABs:  partially or completely used   ; 0 / 1,539 ( 0 % )   ;
; User inserted logic elements                ; 0                   ;
; Virtual pins                                ; 0                   ;
; I/O pins                                    ; 4 / 216 ( 2 % )     ;
;     -- Clock pins                           ; 0 / 8 ( 0 % )       ;
;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )       ;
; Global signals                              ; 0                   ;
; M9Ks                                        ; 0 / 66 ( 0 % )      ;
; Total memory bits                           ; 0 / 608,256 ( 0 % ) ;
; Total RAM block bits                        ; 0 / 608,256 ( 0 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 132 ( 0 % )     ;
; PLLs                                        ; 0 / 4 ( 0 % )       ;
; Global clocks                               ; 0 / 20 ( 0 % )      ;
; Impedance control blocks                    ; 0 / 4 ( 0 % )       ;
; Average interconnect usage                  ; 0%                  ;
; Peak interconnect usage                     ; 0%                  ;
; Maximum fan-out node                        ; sdiout~output       ;
; Maximum fan-out                             ; 2                   ;
; Highest non-global fan-out signal           ; sdiout~output       ;
; Highest non-global fan-out                  ; 1                   ;
; Total fan-out                               ; 10                  ;
; Average fan-out                             ; 0.63                ;
+---------------------------------------------+---------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.