📄 sditest.sta.rpt
字号:
Nothing to report.
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; Fast 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
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; Fast 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
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; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
--------------------------------------------
; Fast 1200mV 0C Model Minimum Pulse Width ;
--------------------------------------------
Nothing to report.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+---------------+--------------+---------------+----------------+------------------+--------+--------------+--------------------+--------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; Pin ; I/O Standard ; Near Series R ; Near Pull-up R ; Near Pull-down R ; Near C ; Tline Length ; Tline L per Length ; Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ;
+---------------+--------------+---------------+----------------+------------------+--------+--------------+--------------------+--------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; short ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;
; ~ALTERA_nCEO~ ; 2.5 V ; short ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;
+---------------+--------------+---------------+----------------+------------------+--------+--------------+--------------------+--------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+-------------------------------------+-------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+------------------------------------+------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Margin on Rise at FPGA Pin ; Ringback Margin on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Margin on Rise at Far-end ; Ringback Margin on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+-------------------------------------+-------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+------------------------------------+------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.58e-007 V ; 3.13 V ; -0.0968 V ; 0.165 V ; 0.126 V ; 3.14e-010 s ; 3.98e-010 s ; Yes ; Yes ; 3.08 V ; 2.58e-007 V ; 3.13 V ; -0.0968 V ; 0.165 V ; 0.126 V ; 3.14e-010 s ; 3.98e-010 s ; Yes ; Yes ;
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.05e-007 V ; 2.34 V ; -0.00742 V ; 0.108 V ; 0.0269 V ; 6.58e-010 s ; 8.21e-010 s ; Yes ; Yes ; 2.32 V ; 4.05e-007 V ; 2.34 V ; -0.00742 V ; 0.108 V ; 0.0269 V ; 6.58e-010 s ; 8.21e-010 s ; Yes ; Yes ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+-------------------------------------+-------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+------------------------------------+------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+-------------------------------------+-------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+------------------------------------+------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Margin on Rise at FPGA Pin ; Ringback Margin on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Margin on Rise at Far-end ; Ringback Margin on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+-------------------------------------+-------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+------------------------------------+------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.53e-008 V ; 3.66 V ; -0.241 V ; 0.408 V ; 0.303 V ; 1.57e-010 s ; 2.12e-010 s ; No ; Yes ; 3.46 V ; 6.53e-008 V ; 3.66 V ; -0.241 V ; 0.408 V ; 0.303 V ; 1.57e-010 s ; 2.12e-010 s ; No ; Yes ;
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; -1.43e-005 V ; 2.7 V ; -0.0125 V ; 0.272 V ; 0.0342 V ; 3.19e-010 s ; 4.96e-010 s ; No ; Yes ; 2.62 V ; -1.43e-005 V ; 2.7 V ; -0.0125 V ; 0.272 V ; 0.0342 V ; 3.19e-010 s ; 4.96e-010 s ; No ; Yes ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+-------------------------------------+-------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+------------------------------------+------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-------------------
; Clock Transfers ;
-------------------
No clock transfers to report.
---------------
; Report TCCS ;
---------------
No LVDS transmitter found in design.
---------------
; Report RSKM ;
---------------
No LVDS receiver found in design.
+------------------------------------------------+
; Unconstrained Paths ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 1 ; 1 ;
; Unconstrained Input Port Paths ; 2 ; 2 ;
; Unconstrained Output Ports ; 0 ; 0 ;
; Unconstrained Output Port Paths ; 0 ; 0 ;
+---------------------------------+-------+------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version
Info: Processing started: Thu Jun 12 17:56:29 2008
Info: Command: quartus_sta sditest -c sditest
Info: qsta_default_script.tcl version: 25.0.1.4
Critical Warning: SDC file not found: 'sditest.sdc'. An SDC file is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the compiler will not properly optimize the design
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Warning: No clocks defined in design.
Warning: Command report_clocks could not find any constraints or exceptions to report
Info: Analyzing Slow 1200mV 85C Model
Warning: Command report_clock_fmax_summary could not find any constraints or exceptions to report
Info: No setup paths to report
Info: No hold paths to report
Info: No recovery paths to report
Info: No removal paths to report
Warning: Command report_min_pulse_width could not find any constraints or exceptions to report
Info: Analyzing Slow 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Warning: No clocks defined in design.
Warning: Command report_clock_fmax_summary could not find any constraints or exceptions to report
Info: No setup paths to report
Info: No hold paths to report
Info: No recovery paths to report
Info: No removal paths to report
Warning: Command report_min_pulse_width could not find any constraints or exceptions to report
Info: Analyzing Fast 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Warning: No clocks defined in design.
Info: No setup paths to report
Info: No hold paths to report
Info: No recovery paths to report
Info: No removal paths to report
Warning: Command report_min_pulse_width could not find any constraints or exceptions to report
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 10 warnings
Info: Allocated 197 megabytes of memory during processing
Info: Processing ended: Thu Jun 12 17:56:38 2008
Info: Elapsed time: 00:00:09
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