带三态输出的8位d寄存器：74374.txt

VHDL实例

-- Octal D-Type Register with 3-State Outputs
-- Simple model of an Octal D-type register with three-state outputs using two concurrent statements.
-- download from: www.fpga.com.cn & www.pld.com.cn

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY ttl374 IS
   PORT(clock, oebar : IN std_logic; 
        data : IN std_logic_vector(7 DOWNTO 0);
        qout : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY ttl374;

ARCHITECTURE using_1164 OF ttl374 IS
   --internal flip-flop outputs
   SIGNAL qint : std_logic_vector(7 DOWNTO 0);
BEGIN
   qint <= data WHEN rising_edge(clock); --d-type flip flops
   qout <= qint WHEN oebar = '0' ELSE "ZZZZZZZZ"; --three-state buffers
END ARCHITECTURE using_1164;