条件赋值：使用when else语句.vhd

来自「VHDL实例」· VHDL 代码 · 共 23 行

-- Conditional Signal Assignment
-- download from: www.pld.com.cn & www.fpga.com.cn 

Library IEEE ;
use IEEE.std_logic_1164.all ;

ENTITY condsig IS
	PORT
	(
		input0, input1, sel	: IN  BIT;
		output				: OUT BIT
	);
END condsig;

ARCHITECTURE maxpld OF condsig IS
BEGIN

	output <= input0 WHEN sel = '0' ELSE input1;
		
END maxpld;