📄 de2_lcm_ccd.tan.summary
字号:
--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------
Type : Worst-case tsu
Slack : N/A
Required Time : None
Actual Time : 6.688 ns
From : DRAM_DQ[13]
To : Sdram_Control_4Port:u6|mDATAOUT[13]
From Clock : --
To Clock : CLOCK_50
Failed Paths : 0
Type : Worst-case tco
Slack : N/A
Required Time : None
Actual Time : 16.141 ns
From : I2C_AV_Config:u9|I2C_Controller:u0|SD_COUNTER[1]~reg0
To : I2C_SCLK
From Clock : CLOCK_50
To Clock : --
Failed Paths : 0
Type : Worst-case tpd
Slack : N/A
Required Time : None
Actual Time : 10.553 ns
From : SW[14]
To : LEDR[14]
From Clock : --
To Clock : --
Failed Paths : 0
Type : Worst-case th
Slack : N/A
Required Time : None
Actual Time : 4.532 ns
From : SW[0]
To : I2C_CCD_Config:u7|mI2C_DATA[0]
From Clock : --
To Clock : CLOCK_50
Failed Paths : 0
Type : Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
Slack : 2.257 ns
Required Time : 100.00 MHz ( period = 10.000 ns )
Actual Time : 129.15 MHz ( period = 7.743 ns )
From : Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[4]
To : Sdram_Control_4Port:u6|mADDR[8]
From Clock : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
To Clock : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
Failed Paths : 0
Type : Clock Setup: 'CLOCK_50'
Slack : 6.676 ns
Required Time : 50.00 MHz ( period = 20.000 ns )
Actual Time : 150.42 MHz ( period = 6.648 ns )
From : I2S_LCM_Config:u8|mI2S_DATA[12]
To : I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA
From Clock : CLOCK_50
To Clock : CLOCK_50
Failed Paths : 0
Type : Clock Setup: 'LCM_PLL:u0|altpll:altpll_component|_clk0'
Slack : 48.026 ns
Required Time : 18.41 MHz ( period = 54.320 ns )
Actual Time : 158.88 MHz ( period = 6.294 ns )
From : Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[8]
To : Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8]
From Clock : LCM_PLL:u0|altpll:altpll_component|_clk0
To Clock : LCM_PLL:u0|altpll:altpll_component|_clk0
Failed Paths : 0
Type : Clock Setup: 'GPIO_1[10]'
Slack : N/A
Required Time : None
Actual Time : 184.03 MHz ( period = 5.434 ns )
From : CCD_Capture:u3|X_Cont[0]
To : RAW2RGB:u4|mCCD_G[10]
From Clock : GPIO_1[10]
To Clock : GPIO_1[10]
Failed Paths : 0
Type : Clock Hold: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
Slack : 0.391 ns
Required Time : 100.00 MHz ( period = 10.000 ns )
Actual Time : N/A
From : Sdram_Control_4Port:u6|ST[0]
To : Sdram_Control_4Port:u6|ST[0]
From Clock : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
To Clock : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
Failed Paths : 0
Type : Clock Hold: 'LCM_PLL:u0|altpll:altpll_component|_clk0'
Slack : 0.391 ns
Required Time : 18.41 MHz ( period = 54.320 ns )
Actual Time : N/A
From : LCM_Controller:u1|MOD_3[0]
To : LCM_Controller:u1|MOD_3[0]
From Clock : LCM_PLL:u0|altpll:altpll_component|_clk0
To Clock : LCM_PLL:u0|altpll:altpll_component|_clk0
Failed Paths : 0
Type : Clock Hold: 'CLOCK_50'
Slack : 0.391 ns
Required Time : 50.00 MHz ( period = 20.000 ns )
Actual Time : N/A
From : Reset_Delay:u2|oRST_1
To : Reset_Delay:u2|oRST_1
From Clock : CLOCK_50
To Clock : CLOCK_50
Failed Paths : 0
Type : Total number of failed paths
Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0
--------------------------------------------------------------------------------------
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -