1_adder.vhd

来自「VHDL常用程序100例 实例丰富 基本上涵盖了常见的例子」· VHDL 代码 · 共 19 行

entity bit_rtl_adder is
   port ( 
	  in1  : bit_vector;
	  in2  : bit_vector;
	  cntl : bit;
	  pout : out bit_vector
   );
end bit_rtl_adder; 
 
architecture func of bit_rtl_adder is
begin
   process(cntl)
   begin
	  if (cntl = '1') then
		 pout <= in1+in2;
      end if;
   end process;
end  func;