📄 quartus32.txt
字号:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY jsq IS
PORT( clk,clear: in STD_LOGIC;
q: out STD_LOGIC_vector(3 downto 0)
);
END jsq;
ARCHITECTURE a OF jsq IS
signal tmp: STD_LOGIC_vector(3 downto 0);
BEGIN
process(clk)
BEGIN
IF clk'event and clk='1' THEN
IF clear='0' THEN
tmp<="0000";
ELSIF tmp="1001" THEN
tmp<="0000";
ELSE
tmp<=tmp+1;
END IF;
END IF;
END PROCESS;
q<=tmp;
END a;
*******************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fpq IS
PORT(
clk:IN STD_LOGIC;
clear: IN STD_LOGIC;
clk_out:OUT STD_LOGIC
);
END fpq;
ARCHITECTURE a OF fpq IS
SIGNAL tmp:INTEGER RANGE 0 TO 7;
BEGIN
p1:PROCESS(clear,clk)
BEGIN
IF clear='0' THEN
tmp<=0;
ELSIF clk'event AND clk='1' THEN
IF tmp=7 THEN
tmp<=0;
ELSE tmp<=tmp+1;
END IF;
IF tmp<4 THEN
clk_out<='0';
ELSE
clk_out<='1';
END IF;
END IF;
END PROCESS p1;
END a;
***************************************************************************
(采用按钮开关)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY led IS
PORT(switch,clk:IN STD_LOGIC;
show:OUT STD_LOGIC_vector(7 downto 0)
);
END led;
ARCHITECTURE a OF led IS
SIGNAL tmp:INTEGER RANGE 0 TO 15;
SIGNAL ctrl:STD_LOGIC;
BEGIN
PROCESS(switch,clk)
BEGIN
IF clk'event and clk='1' THEN
IF switch='1' THEN
ctrl<=NOT ctrl;
ELSE
ctrl<=ctrl;
END IF;
IF ctrl='1' THEN
IF tmp=15 THEN
tmp<=0;
ELSE
tmp<=tmp+1;
END IF;
CASE tmp IS
WHEN 0=>show<="00000000";
WHEN 1=>show<="10000000";
WHEN 2=>show<="01000000";
WHEN 3=>show<="00100000";
WHEN 4=>show<="00010000";
WHEN 5=>show<="00001000";
WHEN 6=>show<="00000100";
WHEN 7=>show<="00000010";
WHEN 8=>show<="00000001";
WHEN 9=>show<="00000010";
WHEN 10=>show<="00000100";
WHEN 11=>show<="00001000";
WHEN 12=>show<="00010000";
WHEN 13=>show<="00100000";
WHEN 14=>show<="01000000";
WHEN 15=>show<="10000000";
WHEN OTHERS=>show<="00000000";
END CASE;
ELSE
IF tmp=15 THEN
tmp<=0;
ELSE
tmp<=tmp+1;
END IF;
CASE tmp IS
WHEN 0=>show<="00011000";
WHEN 1=>show<="00111100";
WHEN 2=>show<="01111110";
WHEN 3=>show<="11111111";
WHEN 4=>show<="01111110";
WHEN 5=>show<="00111100";
WHEN 6=>show<="00011000";
WHEN 7=>show<="00000000";
WHEN 8=>show<="00011000";
WHEN 9=>show<="00111100";
WHEN 10=>show<="01111110";
WHEN 11=>show<="11111111";
WHEN 12=>show<="01111110";
WHEN 13=>show<="00111100";
WHEN 14=>show<="00011000";
WHEN 15=>show<="00000000";
WHEN OTHERS=>show<="00000000";
END CASE;
END IF;
END IF;
END PROCESS;
END a;
(采用当开关)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY led1 IS
PORT(switch,clk:IN STD_LOGIC;
show:OUT STD_LOGIC_vector(7 downto 0)
);
END led1;
ARCHITECTURE a OF led1 IS
SIGNAL tmp:INTEGER RANGE 0 TO 15;
BEGIN
PROCESS(switch,clk)
BEGIN
IF clk'event and clk='1' THEN
IF switch='1' THEN
IF tmp=15 THEN
tmp<=0;
ELSE
tmp<=tmp+1;
END IF;
CASE tmp IS
WHEN 0=>show<="00000000";
WHEN 1=>show<="10000000";
WHEN 2=>show<="01000000";
WHEN 3=>show<="00100000";
WHEN 4=>show<="00010000";
WHEN 5=>show<="00001000";
WHEN 6=>show<="00000100";
WHEN 7=>show<="00000010";
WHEN 8=>show<="00000001";
WHEN 9=>show<="00000010";
WHEN 10=>show<="00000100";
WHEN 11=>show<="00001000";
WHEN 12=>show<="00010000";
WHEN 13=>show<="00100000";
WHEN 14=>show<="01000000";
WHEN 15=>show<="10000000";
WHEN OTHERS=>show<="00000000";
END CASE;
ELSE
IF tmp=15 THEN
tmp<=0;
ELSE
tmp<=tmp+1;
END IF;
CASE tmp IS
WHEN 0=>show<="00011000";
WHEN 1=>show<="00111100";
WHEN 2=>show<="01111110";
WHEN 3=>show<="11111111";
WHEN 4=>show<="01111110";
WHEN 5=>show<="00111100";
WHEN 6=>show<="00011000";
WHEN 7=>show<="00000000";
WHEN 8=>show<="00011000";
WHEN 9=>show<="00111100";
WHEN 10=>show<="01111110";
WHEN 11=>show<="11111111";
WHEN 12=>show<="01111110";
WHEN 13=>show<="00111100";
WHEN 14=>show<="00011000";
WHEN 15=>show<="00000000";
WHEN OTHERS=>show<="00000000";
END CASE;
END IF;
END IF;
END PROCESS;
END a;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -