📄 quartus.txt
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ymq IS
PORT(
a:IN STD_LOGIC_VECTOR(3 downto 0);
b:OUT STD_LOGIC_VECTOR(6 downto 0);
c:OUT STD_LOGIC_VECTOR(5 downto 0)
);
end ymq;
ARCHITECTURE ymq_arch OF ymq IS
BEGIN
c<="111101";
PROCESS(a)
BEGIN
CASE a IS
WHEN"0000" => b<="1111110"; --0
WHEN"0001" => b<="0110000"; --1
WHEN"0010" => b<="1101101"; --2
WHEN"0011" => b<="1111001"; --3
WHEN"0100" => b<="0110011"; --4
WHEN"0101" => b<="1011011"; --5
WHEN"0110" => b<="1011111"; --6
WHEN"0111" => b<="1110000"; --7
WHEN"1000" => b<="1111111"; --8
WHEN"1001" => b<="1111011"; --9
WHEN OTHERS => b<="0000000";
END CASE;
END PROCESS;
END;
****************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY xzq IS
PORT(
a:IN STD_LOGIC_VECTOR(3 downto 0);
b:OUT STD_LOGIC
);
end xzq;
ARCHITECTURE xzq_arch OF xzq IS
BEGIN
PROCESS(a)
BEGIN
CASE a IS
WHEN"0000" => b<='0';
WHEN"0001" => b<='0';
WHEN"0010" => b<='0';
WHEN"0011" => b<='0';
WHEN"0100" => b<='0';
WHEN"0101" => b<='0';
WHEN"0110" => b<='0';
WHEN"0111" => b<='1';
WHEN"1000" => b<='0';
WHEN"1001" => b<='0';
WHEN"1010" => b<='0';
WHEN"1011" => b<='1';
WHEN"1100" => b<='0'; WHEN"1101" => b<='1'; WHEN"1110" => b<='1'; WHEN"1111" => b<='1';
END CASE;
END PROCESS;
END;
******************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY jfq IS
PORT(cin:IN STD_LOGIC;
a,b:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sum:OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
cha:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END jfq;
ARCHITECTURE one of jfq IS
SIGNAL AA,BB,CC:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
PROCESS(a,b,cin)
BEGIN
IF(cin='1')THEN
AA<='0'&a(3 DOWNTO 0);
BB<='0'&b(3 DOWNTO 0);
sum<=AA+BB;
ELSE
AA<='1'&a(3 DOWNTO 0);
BB<='0'&b(3 DOWNTO 0);
CC<=AA-BB;
cha(3 DOWNTO 0)<=CC(3 DOWNTO 0);
END IF;
END PROCESS;
END one;
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