timegen.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- Timegen.vhd
-- Timing generator for ONE_MINUTE and ONE_SECOND
-- timing pulses
-- 
-- ONE_SECOND is used as a clock enable for the TIMEOUT
-- counter in the A_FSM block
--
-- ONE_MINUTE is used as a clock enable signal in the
-- COUNT4 block. When STOPWATCH input is low the 
-- ONE_MINUTE output is switched to the ONE_SECOND 
-- pulse so the COUNT4 block will count seconds 
-- instead of minutes.
--
----------------------------------------------------

Library IEEE;
use IEEE.Std_Logic_1164.all;
-- Check tool workbook for compatibility with the Numeric_std
-- arithmetic package
use IEEE.numeric_std.all; 

entity TIMEGEN is
   port(CLK        : in std_logic;
        RESET      : in std_logic;
        STOPWATCH  : in std_logic;
        ONE_SECOND : out std_logic;
        ONE_MINUTE : out std_logic);
end TIMEGEN;

architecture RTL of TIMEGEN is
   signal ONE_MINUTE_COUNT  : unsigned(13 downto 0);

-- Intermediate signal for ONE_SECOND output, because this is
-- used as mux input in STOPWATCH mode so can't use output directly
   signal SECONDS, MINUTES  : std_logic;

-- Constant which sets the one minute time period based on 256Hz
-- input clock; 256 clock cycles per second, 60 seconds = 1 minute
   constant LIMIT : integer := ((256*60) - 1);

begin
--------------------------------------------------------------
-- Process for base 14-bit counter which is the base reference
-- from which the timing pulses are generated. LIMIT constant sets
-- the time period.
--
-- Mix of integer and std_logic_vector values allowed with the
-- overloaded arithmetic operators in std_logic_unsigned.
--------------------------------------------------------------

   COUNTER: process (CLK,RESET)
   begin
      if RESET = '1' then
         ONE_MINUTE_COUNT <= (others => '0');
      elsif CLK'event and CLK = '1' then 
         if ONE_MINUTE_COUNT = LIMIT then
            ONE_MINUTE_COUNT <= (others => '0');
         else ONE_MINUTE_COUNT <= ONE_MINUTE_COUNT + 1;
         end if;
      end if;
   end process COUNTER;

--------------------------------------------------------------
-- Decode Logic process to create SECONDS and MINUTES internal
-- signals from ONE_MINUTE_COUNT 
--------------------------------------------------------------

   DECODE_LOGIC: process (ONE_MINUTE_COUNT)
   begin
     -- default assignments for signals
     SECONDS <= '0'; 
     MINUTES <= '0';

     if ONE_MINUTE_COUNT = 0 then
       MINUTES <= '1';
     end if;

     if ONE_MINUTE_COUNT(7 downto 0) = 0 then
       SECONDS <= '1';
     end if;
   end process DECODE_LOGIC;


--------------------------------------------------------------
-- Process which generates ONE_SECOND and ONE_MINUTE timing
-- pulses which act as clock enables. In stopwatch ONE_MINUTE 
-- output mux'ed ONE_SECOND output
--------------------------------------------------------------

   OP_REG: process(CLK,RESET)
   begin
      if RESET = '1' then
         ONE_MINUTE <= '0';
         ONE_SECOND <= '0';
      elsif CLK'event and CLK = '1' then

         ONE_SECOND <= SECONDS;

         if STOPWATCH = '0' then 
            ONE_MINUTE <= SECONDS;
         else
            ONE_MINUTE <= MINUTES;
         end if;

      end if;

   end process OP_REG;

end RTL;